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Commit 40abcf77 authored by Jay Cheng's avatar Jay Cheng Committed by Ben Dooks
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i2c: tegra: Add de-bounce cycles. 



This enables debouncing of the I2C lines. The debounce period is
2 * the debounce register field value, in terms of the I2C block's main
clock. The Tegra TRM indicates that a setting yielding >50nS is
desirable. Hence, a setting of 2 => 4 clocks @ 72MHz => ~55nS.

Signed-off-by: default avatarKen Radtke <kradtke@nvidia.com>
[swarren: Added commit description body,
 Fixed 80-column limit, Reverted file permission change]
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent 2078cf3b

drivers/i2c/busses/i2c-tegra.c

+3 −1
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#define BYTES_PER_FIFO_WORD 4



#define I2C_CNFG				0x000

#define I2C_CNFG_DEBOUNCE_CNT_SHIFT		12

#define I2C_CNFG_PACKET_MODE_EN			(1<<10)

#define I2C_CNFG_NEW_MASTER_FSM			(1<<11)

#define I2C_STATUS				0x01C
@@ -328,7 +329,8 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) 
	if (i2c_dev->is_dvc)

		tegra_dvc_init(i2c_dev);



	val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;

	val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |

		(0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);

	i2c_writel(i2c_dev, val, I2C_CNFG);

	i2c_writel(i2c_dev, 0, I2C_INT_MASK);

	clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);