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Commit 40a96350 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-fixes-for-linus' of... 

Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip:
  perf, x86, nmi: Move LVT un-masking into irq handlers
  perf events, x86: Work around the Nehalem AAJ80 erratum
  perf, x86: Fix BTS condition
  ftrace: Build without frame pointers on Microblaze
parents fcc4dc71 2bce5dac

arch/x86/kernel/cpu/perf_event.c

+12 −4
Original line number Diff line number Diff line
@@ -613,8 +613,8 @@ static int x86_setup_perfctr(struct perf_event *event) 
	/*

	 * Branch tracing:

	 */

	if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&

	    (hwc->sample_period == 1)) {

	if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&

	    !attr->freq && hwc->sample_period == 1) {

		/* BTS is not supported by this architecture. */

		if (!x86_pmu.bts_active)

			return -EOPNOTSUPP;
@@ -1288,6 +1288,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs) 


	cpuc = &__get_cpu_var(cpu_hw_events);



	/*

	 * Some chipsets need to unmask the LVTPC in a particular spot

	 * inside the nmi handler.  As a result, the unmasking was pushed

	 * into all the nmi handlers.

	 *

	 * This generic handler doesn't seem to have any issues where the

	 * unmasking occurs so it was left at the top.

	 */

	apic_write(APIC_LVTPC, APIC_DM_NMI);



	for (idx = 0; idx < x86_pmu.num_counters; idx++) {

		if (!test_bit(idx, cpuc->active_mask)) {

			/*
@@ -1374,8 +1384,6 @@ perf_event_nmi_handler(struct notifier_block *self, 
		return NOTIFY_DONE;

	}



	apic_write(APIC_LVTPC, APIC_DM_NMI);



	handled = x86_pmu.handle_irq(args->regs);

	if (!handled)

		return NOTIFY_DONE;

arch/x86/kernel/cpu/perf_event_intel.c

+27 −2
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ struct intel_percore { 
/*

 * Intel PerfMon, used on Core and later.

 */

static const u64 intel_perfmon_event_map[] =

static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =

{

  [PERF_COUNT_HW_CPU_CYCLES]		= 0x003c,

  [PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
@@ -933,6 +933,16 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) 


	cpuc = &__get_cpu_var(cpu_hw_events);



	/*

	 * Some chipsets need to unmask the LVTPC in a particular spot

	 * inside the nmi handler.  As a result, the unmasking was pushed

	 * into all the nmi handlers.

	 *

	 * This handler doesn't seem to have any issues with the unmasking

	 * so it was left at the top.

	 */

	apic_write(APIC_LVTPC, APIC_DM_NMI);



	intel_pmu_disable_all();

	handled = intel_pmu_drain_bts_buffer();

	status = intel_pmu_get_status();
@@ -998,6 +1008,9 @@ intel_bts_constraints(struct perf_event *event) 
	struct hw_perf_event *hwc = &event->hw;

	unsigned int hw_event, bts_event;



	if (event->attr.freq)

		return NULL;



	hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;

	bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
@@ -1409,6 +1422,18 @@ static __init int intel_pmu_init(void) 
		x86_pmu.percore_constraints = intel_nehalem_percore_constraints;

		x86_pmu.enable_all = intel_pmu_nhm_enable_all;

		x86_pmu.extra_regs = intel_nehalem_extra_regs;



		if (ebx & 0x40) {

			/*

			 * Erratum AAJ80 detected, we work it around by using

			 * the BR_MISP_EXEC.ANY event. This will over-count

			 * branch-misses, but it's still much better than the

			 * architectural event which is often completely bogus:

			 */

			intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;



			pr_cont("erratum AAJ80 worked around, ");

		}

		pr_cont("Nehalem events, ");

		break;

arch/x86/kernel/cpu/perf_event_p4.c

+13 −4
Original line number Diff line number Diff line
@@ -950,11 +950,20 @@ static int p4_pmu_handle_irq(struct pt_regs *regs) 
			x86_pmu_stop(event, 0);

	}



	if (handled) {

		/* p4 quirk: unmask it again */

		apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);

	if (handled)

		inc_irq_stat(apic_perf_irqs);

	}



	/*

	 * When dealing with the unmasking of the LVTPC on P4 perf hw, it has

	 * been observed that the OVF bit flag has to be cleared first _before_

	 * the LVTPC can be unmasked.

	 *

	 * The reason is the NMI line will continue to be asserted while the OVF

	 * bit is set.  This causes a second NMI to generate if the LVTPC is

	 * unmasked before the OVF bit is cleared, leading to unknown NMI

	 * messages.

	 */

	apic_write(APIC_LVTPC, APIC_DM_NMI);



	return handled;

}

kernel/trace/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ if FTRACE 
config FUNCTION_TRACER

	bool "Kernel Function Tracer"

	depends on HAVE_FUNCTION_TRACER

	select FRAME_POINTER if !ARM_UNWIND && !S390

	select FRAME_POINTER if !ARM_UNWIND && !S390 && !MICROBLAZE

	select KALLSYMS

	select GENERIC_TRACER

	select CONTEXT_SWITCH_TRACER