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Commit 4078679e authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'qcom-dt-for-3.16' of... 

Merge tag 'qcom-dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into for-next

Merge "Qualcomm ARM Based Device Tree Updates for v3.16" from Kumar Gala:

* Added device tree nodes for pinctrl and SDHC for msm8974 SoC/DB8074 board
* Added binding spec for GSBI configuration node

* tag 'qcom-dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom

:
  soc: qcom: Add device tree binding for GSBI
  ARM: dts: msm: Add SDHC controller nodes for MSM8974 and DB8074 board
  ARM: dts: MSM8974: Add pinctrl node

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 77579afc 08f9234a

Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt

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QCOM GSBI (General Serial Bus Interface) Driver



The GSBI controller is modeled as a node with zero or more child nodes, each

representing a serial sub-node device that is mux'd as part of the GSBI

configuration settings.  The mode setting will govern the input/output mode of

the 4 GSBI IOs.



Required properties:

- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064

- reg: Address range for GSBI registers

- clocks: required clock

- clock-names: must contain "iface" entry

- qcom,mode : indicates MUX value for configuration of the serial interface.

  Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.



Optional properties:

- qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference

  dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.



Required properties if child node exists:

- #address-cells: Must be 1

- #size-cells: Must be 1

- ranges: Must be present



Properties for children:



A GSBI controller node can contain 0 or more child nodes representing serial

devices.  These serial devices can be a QCOM UART, I2C controller, spi

controller, or some combination of aforementioned devices.



See the following for child node definitions:

Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt

Documentation/devicetree/bindings/spi/qcom,spi-qup.txt

Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt



Example for APQ8064:



#include <dt-bindings/soc/qcom,gsbi.h>



	gsbi4@16300000 {

		compatible = "qcom,gsbi-v1.0.0";

		reg = <0x16300000 0x100>;

		clocks = <&gcc GSBI4_H_CLK>;

		clock-names = "iface";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		qcom,mode = <GSBI_PROT_I2C_UART>;

		qcom,crci = <GSBI_CRCI_QUP>;



		/* child nodes go under here */



		i2c_qup4: i2c@16380000 {

		        compatible = "qcom,i2c-qup-v1.1.1";

		        reg = <0x16380000 0x1000>;

		        interrupts = <0 153 0>;



		        clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;

		        clock-names = "core", "iface";



		        clock-frequency = <200000>;



		        #address-cells = <1>;

		        #size-cells = <0>;



		 };



		uart4:	serial@16340000 {

			compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";

			reg = <0x16340000 0x1000>,

				<0x16300000 0x1000>;

			interrupts = <0 152 0x0>;

			clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;

			clock-names = "core", "iface";

			status = "ok";

		};

	};

arch/arm/boot/dts/qcom-apq8074-dragonboard.dts

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@@ -3,4 +3,17 @@ 
/ {

	model = "Qualcomm APQ8074 Dragonboard";

	compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";



	soc: soc {

		sdhci@f9824900 {

			bus-width = <8>;

			non-removable;

			status = "ok";

		};



		sdhci@f98a4900 {

			cd-gpios = <&msmgpio 62 0x1>;

			bus-width = <4>;

		};

	};

};

arch/arm/boot/dts/qcom-msm8974.dtsi

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@@ -192,11 +192,62 @@ 
			clock-names = "core", "iface";

		};



		sdhci@f9824900 {

			compatible = "qcom,sdhci-msm-v4";

			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 0>, <0 138 0>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		sdhci@f98a4900 {

			compatible = "qcom,sdhci-msm-v4";

			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;

			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 0>, <0 221 0>;

			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;

			clock-names = "core", "iface";

			status = "disabled";

		};



		rng@f9bff000 {

			compatible = "qcom,prng";

			reg = <0xf9bff000 0x200>;

			clocks = <&gcc GCC_PRNG_AHB_CLK>;

			clock-names = "core";

		};



		msmgpio: pinctrl@fd510000 {

			compatible = "qcom,msm8974-pinctrl";

			reg = <0xfd510000 0x4000>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			interrupts = <0 208 0>;



			spi8_default: spi8_default {

				mosi {

					pins = "gpio45";

					function = "blsp_spi8";

				};

				miso {

					pins = "gpio46";

					function = "blsp_spi8";

				};

				cs {

					pins = "gpio47";

					function = "blsp_spi8";

				};

				clk {

					pins = "gpio48";

					function = "blsp_spi8";

				};

			};

		};

	};

};

include/dt-bindings/soc/qcom,gsbi.h

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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#ifndef __DT_BINDINGS_QCOM_GSBI_H

#define __DT_BINDINGS_QCOM_GSBI_H



#define GSBI_PROT_IDLE		0

#define GSBI_PROT_I2C_UIM	1

#define GSBI_PROT_I2C		2

#define GSBI_PROT_SPI		3

#define GSBI_PROT_UART_W_FC	4

#define GSBI_PROT_UIM		5

#define GSBI_PROT_I2C_UART	6



#define GSBI_CRCI_QUP		0

#define GSBI_CRCI_UART		1



#endif