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Commit 402cd9f0 authored by Xiang Chen's avatar Xiang Chen Committed by Martin K. Petersen
Browse files

scsi: hisi_sas: add v3 code to fill some more hw function pointers 



Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate,
and phy enable/disable.

Signed-off-by: default avatarJohn Garry <john.garry@huawei.com>
Signed-off-by: default avatarXiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent f771d3b0

drivers/scsi/hisi_sas/hisi_sas_v3_hw.c

+39 −0
Original line number Diff line number Diff line
@@ -129,6 +129,8 @@ 
#define TXID_AUTO				(PORT_BASE + 0xb8)

#define CT3_OFF		1

#define CT3_MSK		(0x1 << CT3_OFF)

#define TX_HARDRST_OFF          2

#define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)

#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)

#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)

#define SAS_SSP_CON_TIMER_CFG		(PORT_BASE + 0x134)
@@ -596,6 +598,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 
	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);

}



static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)

{

	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);



	cfg &= ~PHY_CFG_ENA_MSK;

	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);

}



static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)

{

	config_id_frame_v3_hw(hisi_hba, phy_no);
@@ -603,6 +613,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 
	enable_phy_v3_hw(hisi_hba, phy_no);

}



static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)

{

	disable_phy_v3_hw(hisi_hba, phy_no);

}



static void start_phys_v3_hw(struct hisi_hba *hisi_hba)

{

	int i;
@@ -611,6 +626,26 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba) 
		start_phy_v3_hw(hisi_hba, i);

}



static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)

{

	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];

	u32 txid_auto;



	stop_phy_v3_hw(hisi_hba, phy_no);

	if (phy->identify.device_type == SAS_END_DEVICE) {

		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);

		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,

					txid_auto | TX_HARDRST_MSK);

	}

	msleep(100);

	start_phy_v3_hw(hisi_hba, phy_no);

}



enum sas_linkrate phy_get_max_linkrate_v3_hw(void)

{

	return SAS_LINK_RATE_12_0_GBPS;

}



static void phys_init_v3_hw(struct hisi_hba *hisi_hba)

{

	start_phys_v3_hw(hisi_hba);
@@ -1574,6 +1609,10 @@ static const struct hisi_sas_hw hisi_sas_v3_hw = { 
	.start_delivery = start_delivery_v3_hw,

	.slot_complete = slot_complete_v3_hw,

	.phys_init = phys_init_v3_hw,

	.phy_enable = enable_phy_v3_hw,

	.phy_disable = disable_phy_v3_hw,

	.phy_hard_reset = phy_hard_reset_v3_hw,

	.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,

};



static struct Scsi_Host *