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Commit 401c94a0 authored by Ram Prakash Gupta's avatar Ram Prakash Gupta
Browse files

mmc: sdhci-msm: Switch to required pad voltage for vbias bypass 



Due to hw limitation to sync current, voltage bump up was observed
for sdcc vbias. Switch to required pad voltage for vbias bypass
as hw work around.

Change-Id: I888db2bb093c7a1153649f15167eb8428722256c
Signed-off-by: default avatarRam Prakash Gupta <rampraka@codeaurora.org>
parent 4d997318

drivers/mmc/host/sdhci-msm.c

+50 −7
Original line number Diff line number Diff line
@@ -3133,6 +3133,45 @@ static int sdhci_msm_clear_pwrctl_status(struct sdhci_host *host, u8 value) 
	return ret;

}



static void sdhci_msm_vbias_bypass_wa(struct sdhci_host *host)

{

	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);

	struct sdhci_msm_host *msm_host = pltfm_host->priv;

	const struct sdhci_msm_offset *msm_host_offset =

					msm_host->offset;

	struct mmc_host *mmc = host->mmc;

	u32 config;

	int card_detect = 0;



	if (mmc->ops->get_cd)

		card_detect = mmc->ops->get_cd(mmc);



	config = readl_relaxed(host->ioaddr +

			msm_host_offset->CORE_VENDOR_SPEC);

	/*

	 * Following cases are covered.

	 * 1. Card Probe

	 * 2. Card suspend

	 * 3. Card Resume

	 * 4. Card remove

	 */

	if ((mmc->card == NULL) && card_detect &&

		(mmc->ios.power_mode == MMC_POWER_UP))

		config &= ~CORE_IO_PAD_PWR_SWITCH;

	else if (mmc->card && card_detect &&

			(mmc->ios.power_mode == MMC_POWER_OFF))

		config |= CORE_IO_PAD_PWR_SWITCH;

	else if (mmc->card && card_detect &&

			(mmc->ios.power_mode == MMC_POWER_UP))

		config &= ~CORE_IO_PAD_PWR_SWITCH;

	else if (mmc->card == NULL && !card_detect &&

			(mmc->ios.power_mode == MMC_POWER_OFF))

		config |= CORE_IO_PAD_PWR_SWITCH;



	writel_relaxed(config, host->ioaddr +

				msm_host_offset->CORE_VENDOR_SPEC);

}



static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)

{

	struct sdhci_host *host = (struct sdhci_host *)data;
@@ -3221,17 +3260,21 @@ static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data) 
	mb();

	if ((io_level & REQ_IO_HIGH) &&

			(msm_host->caps_0 & CORE_3_0V_SUPPORT) &&

			!msm_host->core_3_0v_support)

			!msm_host->core_3_0v_support) {

		if (msm_host->vbias_skip_wa)

			sdhci_msm_vbias_bypass_wa(host);

		else

			writel_relaxed((readl_relaxed(host->ioaddr +

					msm_host_offset->CORE_VENDOR_SPEC) &

					~CORE_IO_PAD_PWR_SWITCH), host->ioaddr +

					msm_host_offset->CORE_VENDOR_SPEC);

	else if ((io_level & REQ_IO_LOW) ||

			(msm_host->caps_0 & CORE_1_8V_SUPPORT))

	} else if ((io_level & REQ_IO_LOW) ||

			(msm_host->caps_0 & CORE_1_8V_SUPPORT)) {

		writel_relaxed((readl_relaxed(host->ioaddr +

				msm_host_offset->CORE_VENDOR_SPEC) |

				CORE_IO_PAD_PWR_SWITCH), host->ioaddr +

				msm_host_offset->CORE_VENDOR_SPEC);

	}

	/*

	 * SDHC has core_mem and hc_mem device memory and these memory

	 * addresses do not fall within 1KB region. Hence, any update to