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Commit 3fd44736 authored by Kim Phillips's avatar Kim Phillips Committed by Kumar Gala
Browse files

powerpc/fsl: update crypto node definition and device tree instances 



delete obsolete device-type property, delete model property
(use compatible property instead), prepend "fsl," to Freescale
specific properties. Add nodes to device trees that are missing them,
and fix broken property values in other trees.

Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent d0fc2eaa

Documentation/powerpc/dts-bindings/fsl/sec.txt

0 → 100644
+68 −0
Original line number Diff line number Diff line 
Freescale SoC SEC Security Engines



Required properties:



- compatible : Should contain entries for this and backward compatible

  SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"

- reg : Offset and length of the register set for the device

- interrupts : the SEC's interrupt number

- fsl,num-channels : An integer representing the number of channels

  available.

- fsl,channel-fifo-len : An integer representing the number of

  descriptor pointers each channel fetch fifo can hold.

- fsl,exec-units-mask : The bitmask representing what execution units

  (EUs) are available. It's a single 32-bit cell. EU information

  should be encoded following the SEC's Descriptor Header Dword

  EU_SEL0 field documentation, i.e. as follows:



	bit 0  = reserved - should be 0

	bit 1  = set if SEC has the ARC4 EU (AFEU)

	bit 2  = set if SEC has the DES/3DES EU (DEU)

	bit 3  = set if SEC has the message digest EU (MDEU/MDEU-A)

	bit 4  = set if SEC has the random number generator EU (RNG)

	bit 5  = set if SEC has the public key EU (PKEU)

	bit 6  = set if SEC has the AES EU (AESU)

	bit 7  = set if SEC has the Kasumi EU (KEU)

	bit 8  = set if SEC has the CRC EU (CRCU)

	bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)



remaining bits are reserved for future SEC EUs.



- fsl,descriptor-types-mask : The bitmask representing what descriptors

  are available. It's a single 32-bit cell. Descriptor type information

  should be encoded following the SEC's Descriptor Header Dword DESC_TYPE

  field documentation, i.e. as follows:



	bit 0  = set if SEC supports the aesu_ctr_nonsnoop desc. type

	bit 1  = set if SEC supports the ipsec_esp descriptor type

	bit 2  = set if SEC supports the common_nonsnoop desc. type

	bit 3  = set if SEC supports the 802.11i AES ccmp desc. type

	bit 4  = set if SEC supports the hmac_snoop_no_afeu desc. type

	bit 5  = set if SEC supports the srtp descriptor type

	bit 6  = set if SEC supports the non_hmac_snoop_no_afeu desc.type

	bit 7  = set if SEC supports the pkeu_assemble descriptor type

	bit 8  = set if SEC supports the aesu_key_expand_output desc.type

	bit 9  = set if SEC supports the pkeu_ptmul descriptor type

	bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type

	bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type



  ..and so on and so forth.



Optional properties:



- interrupt-parent : the phandle for the interrupt controller that

  services interrupts for this device.



Example:



	/* MPC8548E */

	crypto@30000 {

		compatible = "fsl,sec2.1", "fsl,sec2.0";

		reg = <0x30000 0x10000>;

		interrupts = <29 2>;

		interrupt-parent = <&mpic>;

		fsl,num-channels = <4>;

		fsl,channel-fifo-len = <24>;

		fsl,exec-units-mask = <0xfe>;

		fsl,descriptor-types-mask = <0x12b0ebf>;

	};

arch/powerpc/boot/dts/mpc8272ads.dts

+7 −14
Original line number Diff line number Diff line
@@ -237,22 +237,15 @@ 
			compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";

		};



/* May need to remove if on a part without crypto engine */

		crypto@30000 {

			device_type = "crypto";

			model = "SEC2";

			compatible = "fsl,mpc8272-talitos-sec2",

			             "fsl,talitos-sec2",

			             "fsl,talitos",

			             "talitos";

			reg = <0x30000 0x10000>;

			interrupts = <11 8>;

			compatible = "fsl,sec1.0";

			reg = <0x40000 0x13000>;

			interrupts = <47 0x8>;

			interrupt-parent = <&PIC>;

			num-channels = <4>;

			channel-fifo-len = <24>;

			exec-units-mask = <0x7e>;

/* desc mask is for rev1.x, we need runtime fixup for >=2.x */

			descriptor-types-mask = <0x1010ebf>;

			fsl,num-channels = <4>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0x7e>;

			fsl,descriptor-types-mask = <0x1010415>;

		};

	};

arch/powerpc/boot/dts/mpc8313erdb.dts

+6 −9
Original line number Diff line number Diff line
@@ -254,17 +254,14 @@ 
		};



		crypto@30000 {

			device_type = "crypto";

			model = "SEC2";

			compatible = "talitos";

			reg = <0x30000 0x7000>;

			compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";

			reg = <0x30000 0x10000>;

			interrupts = <11 0x8>;

			interrupt-parent = <&ipic>;

			/* Rev. 2.2 */

			num-channels = <1>;

			channel-fifo-len = <24>;

			exec-units-mask = <0x0000004c>;

			descriptor-types-mask = <0x0122003f>;

			fsl,num-channels = <1>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0x4c>;

			fsl,descriptor-types-mask = <0x0122003f>;

		};



		/* IPIC

arch/powerpc/boot/dts/mpc8315erdb.dts

+7 −8
Original line number Diff line number Diff line
@@ -241,17 +241,16 @@ 
		};



		crypto@30000 {

			model = "SEC3";

			device_type = "crypto";

			compatible = "talitos";

			compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",

				     "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",

				     "fsl,sec2.0";

			reg = <0x30000 0x10000>;

			interrupts = <11 0x8>;

			interrupt-parent = <&ipic>;

			/* Rev. 3.0 geometry */

			num-channels = <4>;

			channel-fifo-len = <24>;

			exec-units-mask = <0x000001fe>;

			descriptor-types-mask = <0x03ab0ebf>;

			fsl,num-channels = <4>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0x97c>;

			fsl,descriptor-types-mask = <0x3ab0abf>;

		};



		sata@18000 {

arch/powerpc/boot/dts/mpc832x_mds.dts

+6 −9
Original line number Diff line number Diff line
@@ -150,17 +150,14 @@ 
		};



		crypto@30000 {

			device_type = "crypto";

			model = "SEC2";

			compatible = "talitos";

			reg = <0x30000 0x7000>;

			compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";

			reg = <0x30000 0x10000>;

			interrupts = <11 0x8>;

			interrupt-parent = <&ipic>;

			/* Rev. 2.2 */

			num-channels = <1>;

			channel-fifo-len = <24>;

			exec-units-mask = <0x0000004c>;

			descriptor-types-mask = <0x0122003f>;

			fsl,num-channels = <1>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0x4c>;

			fsl,descriptor-types-mask = <0x0122003f>;

		};



		ipic: pic@700 {