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Commit 3f92a054 authored by Xing Zheng's avatar Xing Zheng Committed by Heiko Stuebner
Browse files

clk: rockchip: assign more necessary rk3399 clock ids 



Assign newly added clock ids.

Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent de87985e

drivers/clk/rockchip/clk-rk3399.c

+6 −6
Original line number Diff line number Diff line
@@ -554,7 +554,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,

			RK3399_CLKGATE_CON(5), 5, GFLAGS),



	MUX(0, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,

	MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,

			RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),

	GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLK_IGNORE_UNUSED,

			RK3399_CLKGATE_CON(5), 6, GFLAGS),
@@ -780,7 +780,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKGATE_CON(16), 1, GFLAGS),



	/* rga */

	COMPOSITE(0, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,

	COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, CLK_IGNORE_UNUSED,

			RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK3399_CLKGATE_CON(4), 10, GFLAGS),
@@ -896,7 +896,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,

			RK3399_CLKGATE_CON(6), 2, GFLAGS),



	COMPOSITE_NOMUX(0, "clk_pciephy_ref100m", "npll", CLK_IGNORE_UNUSED,

	COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", CLK_IGNORE_UNUSED,

			RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,

			RK3399_CLKGATE_CON(12), 6, GFLAGS),

	MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
@@ -1191,10 +1191,10 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
			RK3399_CLKGATE_CON(10), 15, GFLAGS),



	/* isp */

	COMPOSITE(0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,

	COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,

			RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK3399_CLKGATE_CON(12), 8, GFLAGS),

	COMPOSITE_NOMUX(0, "hclk_isp0", "aclk_isp0", 0,

	COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,

			RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,

			RK3399_CLKGATE_CON(12), 9, GFLAGS),
@@ -1217,7 +1217,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { 
	COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,

			RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,

			RK3399_CLKGATE_CON(12), 10, GFLAGS),

	COMPOSITE_NOMUX(0, "hclk_isp1", "aclk_isp1", 0,

	COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,

			RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,

			RK3399_CLKGATE_CON(12), 11, GFLAGS),