Merge "clk: qcom: alpha-pll: Update the Lucid PLL registers for debug" (3f6a54bd) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/clk/qcom/clk-alpha-pll.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -161,7 +161,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
		#define LUCID_PCAL_DONE BIT(27)

		/* ZONDA PLL specific offsets */
		#define ZONDA_PLL_OUT_MASK 0x9
		#define ZONDA_PLL_OUT_MASK 0xF
		#define ZONDA_STAY_IN_CFA BIT(16)
		#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)

		@@ -1850,7 +1850,8 @@ static void clk_alpha_pll_lucid_list_registers(struct seq_file *f,
		{"PLL_CONFIG_CTL_U", 0x1c},
		{"PLL_CONFIG_CTL_U1", 0x20},
		{"PLL_TEST_CTL", 0x24},
		{"PLL_TEST_CTL_U1", 0x28},
		{"PLL_TEST_CTL_U", 0x28},
		{"PLL_TEST_CTL_U1", 0x2C},
		{"PLL_STATUS", 0x30},
		{"PLL_ALPHA_VAL", 0x40},
		};

drivers/clk/qcom/gcc-lito.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1124,7 +1124,7 @@ static struct clk_branch gcc_cpuss_rbcpr_clk = {

		static struct clk_branch gcc_ddrss_gpu_axi_clk = {
		.halt_reg = 0x71154,
		.halt_check = BRANCH_HALT,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x71154,
		.enable_mask = BIT(0),
		@@ -1327,7 +1327,7 @@ static struct clk_branch gcc_gpu_iref_clk = {

		static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
		.halt_reg = 0x7100c,
		.halt_check = BRANCH_HALT,
		.halt_check = BRANCH_VOTED,
		.clkr = {
		.enable_reg = 0x7100c,
		.enable_mask = BIT(0),

drivers/clk/qcom/gpucc-lito.c

+0 −61

Original line number	Diff line number	Diff line
		@@ -63,20 +63,6 @@ static const char * const gpu_cc_parent_names_0[] = {
		"core_bi_pll_test_se",
		};

		static const struct parent_map gpu_cc_parent_map_1[] = {
		{ P_BI_TCXO, 0 },
		{ P_GPLL0_OUT_MAIN, 5 },
		{ P_GPLL0_OUT_MAIN_DIV, 6 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const char * const gpu_cc_parent_names_1[] = {
		"bi_tcxo",
		"gcc_gpu_gpll0_clk_src",
		"gcc_gpu_gpll0_div_clk_src",
		"core_bi_pll_test_se",
		};

		static struct pll_vco lucid_vco[] = {
		{ 249600000, 2000000000, 0 },
		};
		@@ -143,33 +129,6 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
		},
		};

		static const struct freq_tbl ftbl_gpu_cc_rbcpr_clk_src[] = {
		F(19200000, P_BI_TCXO, 1, 0, 0),
		F(50000000, P_GPLL0_OUT_MAIN_DIV, 6, 0, 0),
		{ }
		};

		static struct clk_rcg2 gpu_cc_rbcpr_clk_src = {
		.cmd_rcgr = 0x10b0,
		.mnd_width = 0,
		.hid_width = 5,
		.parent_map = gpu_cc_parent_map_1,
		.freq_tbl = ftbl_gpu_cc_rbcpr_clk_src,
		.enable_safe_config = true,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_rbcpr_clk_src",
		.parent_names = gpu_cc_parent_names_1,
		.num_parents = 4,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOWER] = 19200000,
		[VDD_NOMINAL] = 50000000},
		},
		};

		static struct clk_branch gpu_cc_ahb_clk = {
		.halt_reg = 0x1078,
		.halt_check = BRANCH_HALT_DELAY,
		@@ -298,24 +257,6 @@ static struct clk_branch gpu_cc_gx_vsense_clk = {
		},
		};

		static struct clk_branch gpu_cc_rbcpr_clk = {
		.halt_reg = 0x10f0,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x10f0,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gpu_cc_rbcpr_clk",
		.parent_names = (const char *[]){
		"gpu_cc_rbcpr_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gpu_cc_sleep_clk = {
		.halt_reg = 0x1090,
		.halt_check = BRANCH_HALT_DELAY,
		@@ -354,8 +295,6 @@ static struct clk_regmap *gpu_cc_lito_clocks[] = {
		[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
		[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
		[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
		[GPU_CC_RBCPR_CLK] = &gpu_cc_rbcpr_clk.clkr,
		[GPU_CC_RBCPR_CLK_SRC] = &gpu_cc_rbcpr_clk_src.clkr,
		[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
		[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
		};

include/dt-bindings/clock/qcom,gpucc-lito.h

+2 −4

Original line number	Diff line number	Diff line
		@@ -16,9 +16,7 @@
		#define GPU_CC_GX_GMU_CLK 8
		#define GPU_CC_GX_VSENSE_CLK 9
		#define GPU_CC_PLL1 10
		#define GPU_CC_RBCPR_CLK 11
		#define GPU_CC_RBCPR_CLK_SRC 12
		#define GPU_CC_SLEEP_CLK 13
		#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
		#define GPU_CC_SLEEP_CLK 11
		#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 12

		#endif