Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3f34d958 authored by Jubin John's avatar Jubin John Committed by Doug Ledford
Browse files

staging/rdma/hfi1: Use BIT_ULL macro 



Use BIT_ULL macro to fix checkpatch check:
CHECK: Prefer using the BIT_ULL macro

Reviewed-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Reviewed-by: default avatarMike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: default avatarJubin John <jubin.john@intel.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent 58721b8f

drivers/staging/rdma/hfi1/chip.h

+8 −8
Original line number Diff line number Diff line
@@ -93,15 +93,15 @@ 
#define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)



/* PBC flags */

#define PBC_INTR		(1ull << 31)

#define PBC_INTR		BIT_ULL(31)

#define PBC_DC_INFO_SHIFT	(30)

#define PBC_DC_INFO		(1ull << PBC_DC_INFO_SHIFT)

#define PBC_TEST_EBP	(1ull << 29)

#define PBC_PACKET_BYPASS	(1ull << 28)

#define PBC_CREDIT_RETURN	(1ull << 25)

#define PBC_INSERT_BYPASS_ICRC (1ull << 24)

#define PBC_TEST_BAD_ICRC	(1ull << 23)

#define PBC_FECN		(1ull << 22)

#define PBC_DC_INFO		BIT_ULL(PBC_DC_INFO_SHIFT)

#define PBC_TEST_EBP		BIT_ULL(29)

#define PBC_PACKET_BYPASS	BIT_ULL(28)

#define PBC_CREDIT_RETURN	BIT_ULL(25)

#define PBC_INSERT_BYPASS_ICRC	BIT_ULL(24)

#define PBC_TEST_BAD_ICRC	BIT_ULL(23)

#define PBC_FECN		BIT_ULL(22)



/* PbcInsertHcrc field settings */

#define PBC_IHCRC_LKDETH 0x0	/* insert @ local KDETH offset */

drivers/staging/rdma/hfi1/eprom.c

+1 −1
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ 
#define COUNT_DELAY_SEC(n) ((n) * (1000000 / WAIT_SLEEP_US))



/* GPIO pins */

#define EPROM_WP_N (1ull << 14)	/* EPROM write line */

#define EPROM_WP_N BIT_ULL(14)	/* EPROM write line */



/*

 * Use the EP mutex to guard against other callers from within the driver.

drivers/staging/rdma/hfi1/sdma.h

+4 −4
Original line number Diff line number Diff line
@@ -107,8 +107,8 @@ 
/*

 * Bits defined in the send DMA descriptor.

 */

#define SDMA_DESC0_FIRST_DESC_FLAG      (1ULL << 63)

#define SDMA_DESC0_LAST_DESC_FLAG       (1ULL << 62)

#define SDMA_DESC0_FIRST_DESC_FLAG      BIT_ULL(63)

#define SDMA_DESC0_LAST_DESC_FLAG       BIT_ULL(62)

#define SDMA_DESC0_BYTE_COUNT_SHIFT     48

#define SDMA_DESC0_BYTE_COUNT_WIDTH     14

#define SDMA_DESC0_BYTE_COUNT_MASK \
@@ -152,8 +152,8 @@ 
	((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1)

#define SDMA_DESC1_GENERATION_SMASK \

	(SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT)

#define SDMA_DESC1_INT_REQ_FLAG         (1ULL << 1)

#define SDMA_DESC1_HEAD_TO_HOST_FLAG    (1ULL << 0)

#define SDMA_DESC1_INT_REQ_FLAG         BIT_ULL(1)

#define SDMA_DESC1_HEAD_TO_HOST_FLAG    BIT_ULL(0)



enum sdma_states {

	sdma_state_s00_hw_down,