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Commit 3eb61566 authored by Andrew Bresticker's avatar Andrew Bresticker Committed by Thierry Reding
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clk: tegra: pll: Fix potential sleeping-while-atomic 



Since the ->enable() callback is called with a spinlock held, we cannot
call potentially blocking functions such as clk_get_rate() or
clk_get_parent(), so use the unlocked versions instead.

Signed-off-by: default avatarAndrew Bresticker <abrestic@chromium.org>
[rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as
it isn't present upstream]
Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 736971be

drivers/clk/tegra/clk-pll.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -880,7 +880,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) 
static int clk_plle_enable(struct clk_hw *hw)

static int clk_plle_enable(struct clk_hw *hw)

{

{

	struct tegra_clk_pll *pll = to_clk_pll(hw);

	struct tegra_clk_pll *pll = to_clk_pll(hw);

	unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));

	unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));

	struct tegra_clk_pll_freq_table sel;

	struct tegra_clk_pll_freq_table sel;

	u32 val;

	u32 val;

	int err;

	int err;
@@ -1378,7 +1378,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) 
	u32 val;

	u32 val;

	int ret;

	int ret;

	unsigned long flags = 0;

	unsigned long flags = 0;

	unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));

	unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));





	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

		return -EINVAL;

		return -EINVAL;
@@ -2014,7 +2014,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) 
	u32 val;

	u32 val;

	int ret;

	int ret;

	unsigned long flags = 0;

	unsigned long flags = 0;

	unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk));

	unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));





	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))

		return -EINVAL;

		return -EINVAL;