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Commit 3e5907a1 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Laurent Pinchart
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drm: rcar-du: lvds: Fix LVDCR1 for R-Car gen3 



The LVDCR1 register for the R-Car gen3 SoCs was documented as having the
layout different from the gen2 SoCs in  the early R-Car gen3 manuals but
since v0.52 the LVDCR1 layout is described as being the same as on the gen2
SoCs; the old CHn control values are said to be prohibited now (and there
seems to be no valid output signal when they are used).

Fixes: 6bc2e15c ("drm: rcar-du: lvds: Add R-Car Gen3 support")
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
parent 9ff3e797

drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c

+4 −6
Original line number Diff line number Diff line
@@ -70,9 +70,8 @@ static void rcar_du_lvdsenc_start_gen2(struct rcar_du_lvdsenc *lvds, 


	/* Turn all the channels on. */

	rcar_lvds_write(lvds, LVDCR1,

			LVDCR1_CHSTBY_GEN2(3) | LVDCR1_CHSTBY_GEN2(2) |

			LVDCR1_CHSTBY_GEN2(1) | LVDCR1_CHSTBY_GEN2(0) |

			LVDCR1_CLKSTBY_GEN2);

			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |

			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);



	/*

	 * Turn the PLL on, wait for the startup delay, and turn the output
@@ -109,9 +108,8 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, 


	/* Turn all the channels on. */

	rcar_lvds_write(lvds, LVDCR1,

			LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |

			LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |

			LVDCR1_CLKSTBY_GEN3);

			LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |

			LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);



	/*

	 * Turn the PLL on, set it to LVDS normal mode, wait for the startup

drivers/gpu/drm/rcar-du/rcar_lvds_regs.h

+2 −4
Original line number Diff line number Diff line
@@ -26,10 +26,8 @@ 


#define LVDCR1				0x0004

#define LVDCR1_CKSEL			(1 << 15)		/* Gen2 only */

#define LVDCR1_CHSTBY_GEN2(n)		(3 << (2 + (n) * 2))	/* Gen2 only */

#define LVDCR1_CHSTBY_GEN3(n)		(1 << (2 + (n) * 2))	/* Gen3 only */

#define LVDCR1_CLKSTBY_GEN2		(3 << 0)		/* Gen2 only */

#define LVDCR1_CLKSTBY_GEN3		(1 << 0)		/* Gen3 only */

#define LVDCR1_CHSTBY(n)		(3 << (2 + (n) * 2))

#define LVDCR1_CLKSTBY			(3 << 0)



#define LVDPLLCR			0x0008

#define LVDPLLCR_CEEN			(1 << 14)