clk: stm32h7: Add stm32h743 clock driver

STMicroelectronics STM32H7 Reset and Clock Controller

=====================================================

The RCC IP is both a reset and a clock controller.

Please refer to clock-bindings.txt for common clock controller binding usage.

Please also refer to reset.txt for common reset controller binding usage.

Required properties:

- compatible: Should be:

  "st,stm32h743-rcc"

- reg: should be register base and length as documented in the

  datasheet

- #reset-cells: 1, see below

- #clock-cells : from common clock binding; shall be set to 1

- clocks: External oscillator clock phandle

  - high speed external clock signal (HSE)

  - low speed external clock signal (LSE)

  - external I2S clock (I2S_CKIN)

Optional properties:

- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain

  write protection (RTC clock).

Example:

	rcc: reset-clock-controller@58024400 {

		compatible = "st,stm32h743-rcc", "st,stm32-rcc";

		reg = <0x58024400 0x400>;

		#reset-cells = <1>;

		#clock-cells = <2>;

		clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;

		st,syscfg = <&pwrcfg>;

};

The peripheral clock consumer should specify the desired clock by

having the clock ID in its "clocks" phandle cell.

Example:

		timer5: timer@40000c00 {

			compatible = "st,stm32-timer";

			reg = <0x40000c00 0x400>;

			interrupts = <50>;

			clocks = <&rcc TIM5_CK>;

		};

Specifying softreset control of devices

=======================================

Device nodes should specify the reset channel required in their "resets"

property, containing a phandle to the reset device node and an index specifying

which channel to use.

The index is the bit number within the RCC registers bank, starting from RCC

base address.

It is calculated as: index = register_offset / 4 * 32 + bit_offset.

Where bit_offset is the bit offset within the register.

For example, for CRC reset:

  crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107

Example:

	timer2 {

		resets	= <&rcc STM32H7_APB1L_RESET(TIM2)>;

	};

obj-$(CONFIG_COMMON_CLK_SI514)		+= clk-si514.o

obj-$(CONFIG_COMMON_CLK_SI570)		+= clk-si570.o

obj-$(CONFIG_ARCH_STM32)		+= clk-stm32f4.o

obj-$(CONFIG_ARCH_STM32)		+= clk-stm32h7.o

obj-$(CONFIG_ARCH_TANGO)		+= clk-tango4.o

obj-$(CONFIG_CLK_TWL6040)		+= clk-twl6040.o

obj-$(CONFIG_ARCH_U300)			+= clk-u300.o

/* SYS, CORE AND BUS CLOCKS */

#define SYS_D1CPRE 0

#define HCLK 1

#define PCLK1 2

#define PCLK2 3

#define PCLK3 4

#define PCLK4 5

#define HSI_DIV 6

#define HSE_1M 7

#define I2S_CKIN 8

#define CK_DSI_PHY 9

#define HSE_CK 10

#define LSE_CK 11

#define CSI_KER_DIV122 12

#define RTC_CK 13

#define CPU_SYSTICK 14

/* OSCILLATOR BANK */

#define OSC_BANK 18

#define HSI_CK 18

#define HSI_KER_CK 19

#define CSI_CK 20

#define CSI_KER_CK 21

#define RC48_CK 22

#define LSI_CK 23

/* MCLOCK BANK */

#define MCLK_BANK 28

#define PER_CK 28

#define PLLSRC 29

#define SYS_CK 30

#define TRACEIN_CK 31

/* ODF BANK */

#define ODF_BANK 32

#define PLL1_P 32

#define PLL1_Q 33

#define PLL1_R 34

#define PLL2_P 35

#define PLL2_Q 36

#define PLL2_R 37

#define PLL3_P 38

#define PLL3_Q 39

#define PLL3_R 40

/* MCO BANK */

#define MCO_BANK 41

#define MCO1 41

#define MCO2 42

/* PERIF BANK */

#define PERIF_BANK 50

#define D1SRAM1_CK 50

#define ITCM_CK 51

#define DTCM2_CK 52

#define DTCM1_CK 53

#define FLITF_CK 54

#define JPGDEC_CK 55

#define DMA2D_CK 56

#define MDMA_CK 57

#define USB2ULPI_CK 58

#define USB1ULPI_CK 59

#define ETH1RX_CK 60

#define ETH1TX_CK 61

#define ETH1MAC_CK 62

#define ART_CK 63

#define DMA2_CK 64

#define DMA1_CK 65

#define D2SRAM3_CK 66

#define D2SRAM2_CK 67

#define D2SRAM1_CK 68

#define HASH_CK 69

#define CRYPT_CK 70

#define CAMITF_CK 71

#define BKPRAM_CK 72

#define HSEM_CK 73

#define BDMA_CK 74

#define CRC_CK 75

#define GPIOK_CK 76

#define GPIOJ_CK 77

#define GPIOI_CK 78

#define GPIOH_CK 79

#define GPIOG_CK 80

#define GPIOF_CK 81

#define GPIOE_CK 82

#define GPIOD_CK 83

#define GPIOC_CK 84

#define GPIOB_CK 85

#define GPIOA_CK 86

#define WWDG1_CK 87

#define DAC12_CK 88

#define WWDG2_CK 89

#define TIM14_CK 90

#define TIM13_CK 91

#define TIM12_CK 92

#define TIM7_CK 93

#define TIM6_CK 94

#define TIM5_CK 95

#define TIM4_CK 96

#define TIM3_CK 97

#define TIM2_CK 98

#define MDIOS_CK 99

#define OPAMP_CK 100

#define CRS_CK 101

#define TIM17_CK 102

#define TIM16_CK 103

#define TIM15_CK 104

#define TIM8_CK 105

#define TIM1_CK 106

#define TMPSENS_CK 107

#define RTCAPB_CK 108

#define VREF_CK 109

#define COMP12_CK 110

#define SYSCFG_CK 111

/* KERNEL BANK */

#define KERN_BANK 120

#define SDMMC1_CK 120

#define QUADSPI_CK 121

#define FMC_CK 122

#define USB2OTG_CK 123

#define USB1OTG_CK 124

#define ADC12_CK 125

#define SDMMC2_CK 126

#define RNG_CK 127

#define ADC3_CK 128

#define DSI_CK 129

#define LTDC_CK 130

#define USART8_CK 131

#define USART7_CK 132

#define HDMICEC_CK 133

#define I2C3_CK 134

#define I2C2_CK 135

#define I2C1_CK 136

#define UART5_CK 137

#define UART4_CK 138

#define USART3_CK 139

#define USART2_CK 140

#define SPDIFRX_CK 141

#define SPI3_CK 142

#define SPI2_CK 143

#define LPTIM1_CK 144

#define FDCAN_CK 145

#define SWP_CK 146

#define HRTIM_CK 147

#define DFSDM1_CK 148

#define SAI3_CK 149

#define SAI2_CK 150

#define SAI1_CK 151

#define SPI5_CK 152

#define SPI4_CK 153

#define SPI1_CK 154

#define USART6_CK 155

#define USART1_CK 156

#define SAI4B_CK 157

#define SAI4A_CK 158

#define LPTIM5_CK 159

#define LPTIM4_CK 160

#define LPTIM3_CK 161

#define LPTIM2_CK 162

#define I2C4_CK 163

#define SPI6_CK 164

#define LPUART1_CK 165

#define STM32H7_MAX_CLKS 166

/*

 * This header provides constants for the STM32H7 RCC IP

 */

#ifndef _DT_BINDINGS_MFD_STM32H7_RCC_H

#define _DT_BINDINGS_MFD_STM32H7_RCC_H

/* AHB3 */

#define STM32H7_RCC_AHB3_MDMA		0

#define STM32H7_RCC_AHB3_DMA2D		4

#define STM32H7_RCC_AHB3_JPGDEC		5

#define STM32H7_RCC_AHB3_FMC		12

#define STM32H7_RCC_AHB3_QUADSPI	14

#define STM32H7_RCC_AHB3_SDMMC1		16

#define STM32H7_RCC_AHB3_CPU		31

#define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))

/* AHB1 */

#define STM32H7_RCC_AHB1_DMA1		0

#define STM32H7_RCC_AHB1_DMA2		1

#define STM32H7_RCC_AHB1_ADC12		5

#define STM32H7_RCC_AHB1_ART		14

#define STM32H7_RCC_AHB1_ETH1MAC	15

#define STM32H7_RCC_AHB1_USB1OTG	25

#define STM32H7_RCC_AHB1_USB2OTG	27

#define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))

/* AHB2 */

#define STM32H7_RCC_AHB2_CAMITF		0

#define STM32H7_RCC_AHB2_CRYPT		4

#define STM32H7_RCC_AHB2_HASH		5

#define STM32H7_RCC_AHB2_RNG		6

#define STM32H7_RCC_AHB2_SDMMC2		9

#define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))

/* AHB4 */

#define STM32H7_RCC_AHB4_GPIOA		0

#define STM32H7_RCC_AHB4_GPIOB		1

#define STM32H7_RCC_AHB4_GPIOC		2

#define STM32H7_RCC_AHB4_GPIOD		3

#define STM32H7_RCC_AHB4_GPIOE		4

#define STM32H7_RCC_AHB4_GPIOF		5

#define STM32H7_RCC_AHB4_GPIOG		6

#define STM32H7_RCC_AHB4_GPIOH		7

#define STM32H7_RCC_AHB4_GPIOI		8

#define STM32H7_RCC_AHB4_GPIOJ		9

#define STM32H7_RCC_AHB4_GPIOK		10

#define STM32H7_RCC_AHB4_CRC		19

#define STM32H7_RCC_AHB4_BDMA		21

#define STM32H7_RCC_AHB4_ADC3		24

#define STM32H7_RCC_AHB4_HSEM		25

#define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))

/* APB3 */

#define STM32H7_RCC_APB3_LTDC		3

#define STM32H7_RCC_APB3_DSI		4

#define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8))

/* APB1L */

#define STM32H7_RCC_APB1L_TIM2		0

#define STM32H7_RCC_APB1L_TIM3		1

#define STM32H7_RCC_APB1L_TIM4		2

#define STM32H7_RCC_APB1L_TIM5		3

#define STM32H7_RCC_APB1L_TIM6		4

#define STM32H7_RCC_APB1L_TIM7		5

#define STM32H7_RCC_APB1L_TIM12		6

#define STM32H7_RCC_APB1L_TIM13		7

#define STM32H7_RCC_APB1L_TIM14		8

#define STM32H7_RCC_APB1L_LPTIM1	9

#define STM32H7_RCC_APB1L_SPI2		14

#define STM32H7_RCC_APB1L_SPI3		15

#define STM32H7_RCC_APB1L_SPDIF_RX	16

#define STM32H7_RCC_APB1L_USART2	17

#define STM32H7_RCC_APB1L_USART3	18

#define STM32H7_RCC_APB1L_UART4		19

#define STM32H7_RCC_APB1L_UART5		20

#define STM32H7_RCC_APB1L_I2C1		21

#define STM32H7_RCC_APB1L_I2C2		22

#define STM32H7_RCC_APB1L_I2C3		23

#define STM32H7_RCC_APB1L_HDMICEC	27

#define STM32H7_RCC_APB1L_DAC12		29

#define STM32H7_RCC_APB1L_USART7	30

#define STM32H7_RCC_APB1L_USART8	31

#define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8))

/* APB1H */

#define STM32H7_RCC_APB1H_CRS		1

#define STM32H7_RCC_APB1H_SWP		2

#define STM32H7_RCC_APB1H_OPAMP		4

#define STM32H7_RCC_APB1H_MDIOS		5

#define STM32H7_RCC_APB1H_FDCAN		8

#define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8))

/* APB2 */

#define STM32H7_RCC_APB2_TIM1		0

#define STM32H7_RCC_APB2_TIM8		1

#define STM32H7_RCC_APB2_USART1		4

#define STM32H7_RCC_APB2_USART6		5

#define STM32H7_RCC_APB2_SPI1		12

#define STM32H7_RCC_APB2_SPI4		13

#define STM32H7_RCC_APB2_TIM15		16

#define STM32H7_RCC_APB2_TIM16		17

#define STM32H7_RCC_APB2_TIM17		18

#define STM32H7_RCC_APB2_SPI5		20

#define STM32H7_RCC_APB2_SAI1		22

#define STM32H7_RCC_APB2_SAI2		23

#define STM32H7_RCC_APB2_SAI3		24

#define STM32H7_RCC_APB2_DFSDM1		28

#define STM32H7_RCC_APB2_HRTIM		29

#define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8))

/* APB4 */

#define STM32H7_RCC_APB4_SYSCFG		1

#define STM32H7_RCC_APB4_LPUART1	3

#define STM32H7_RCC_APB4_SPI6		5

#define STM32H7_RCC_APB4_I2C4		7

#define STM32H7_RCC_APB4_LPTIM2		9

#define STM32H7_RCC_APB4_LPTIM3		10

#define STM32H7_RCC_APB4_LPTIM4		11

#define STM32H7_RCC_APB4_LPTIM5		12

#define STM32H7_RCC_APB4_COMP12		14

#define STM32H7_RCC_APB4_VREF		15

#define STM32H7_RCC_APB4_SAI4		21

#define STM32H7_RCC_APB4_TMPSENS	26

#define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8))

#endif /* _DT_BINDINGS_MFD_STM32H7_RCC_H */