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Commit 3e1e0137 authored by Mohammed Mirza Mandayappurath Manzoor's avatar Mohammed Mirza Mandayappurath Manzoor
Browse files

msm: kgsl: Adjust RBBM_HANG_INT_CNTL register value to increase cycle count 



For some older A6XX chips, GPU may sometimes falsely report a hang
interrupt in case of long running payloads. Increase the number of cycles
for fault detection to avoid false interrupts from the GPU.

Change-Id: I7783e16948cf0af1ac3cad96b2f0149c74dc8723
Signed-off-by: default avatarMohammed Mirza Mandayappurath Manzoor <mmandaya@codeaurora.org>
parent 71d33d32

drivers/gpu/msm/adreno-gpulist.h

+6 −6
Original line number Diff line number Diff line
@@ -792,7 +792,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
	.hwcg_count = ARRAY_SIZE(a630_hwcg_regs),

	.vbif = a630_vbif_regs,

	.vbif_count = ARRAY_SIZE(a630_vbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

};
@@ -891,7 +891,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
	.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),

	.vbif = a615_gbif_regs,

	.vbif_count = ARRAY_SIZE(a615_gbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

};
@@ -1134,7 +1134,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
	.hwcg_count = ARRAY_SIZE(a640_hwcg_regs),

	.vbif = a640_vbif_regs,

	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

	.disable_tseskip = true,

};
@@ -1214,7 +1214,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
	.vbif_count = ARRAY_SIZE(a650_gbif_regs),

	.veto_fal10 = true,

	.pdc_in_aop = true,

	.hang_detect_cycles = 0x3fffff,

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a620_protected_regs,

	.disable_tseskip = true,

};
@@ -1268,7 +1268,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
	.hwcg_count = ARRAY_SIZE(a640_hwcg_regs),

	.vbif = a640_vbif_regs,

	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

	.disable_tseskip = true,

};
@@ -1370,7 +1370,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
	.hwcg_count = ARRAY_SIZE(a615_hwcg_regs),

	.vbif = a615_gbif_regs,

	.vbif_count = ARRAY_SIZE(a615_gbif_regs),

	.hang_detect_cycles = 0x3fffff,

	.hang_detect_cycles = 0xcfffff,

	.protected_regs = a630_protected_regs,

};