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Commit 3dbc65d8 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge 1c29131b on remote branch 

Change-Id: I89db54a98b021857d32ec2505209b239b514191f
parents 540dc815 1c29131b

drivers/char/adsprpc.c

+10 −1
Original line number Diff line number Diff line
@@ -3834,6 +3834,7 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, 
		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"%s%s%s%s%s\n", single_line, single_line,

			single_line, single_line, single_line);

		spin_lock(&me->hlock);

		hlist_for_each_entry_safe(gmaps, n, &me->maps, hn) {

			len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

				"%-20d|0x%-18llX|0x%-18X|0x%-20lX\n\n",
@@ -3841,18 +3842,21 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, 
				(uint32_t)gmaps->size,

				gmaps->va);

		}

		spin_unlock(&me->hlock);

		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"%-20s|%-20s|%-20s|%-20s\n",

			"len", "refs", "raddr", "flags");

		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"%s%s%s%s%s\n", single_line, single_line,

			single_line, single_line, single_line);

		spin_lock(&me->hlock);

		hlist_for_each_entry_safe(gmaps, n, &me->maps, hn) {

			len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

				"0x%-18X|%-20d|%-20lu|%-20u\n",

				(uint32_t)gmaps->len, gmaps->refs,

				gmaps->raddr, gmaps->flags);

		}

		spin_unlock(&me->hlock);

	} else {

		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"\n%s %13s %d\n", "cid", ":", fl->cid);
@@ -3894,12 +3898,14 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, 
			"%s%s%s%s%s\n",

			single_line, single_line, single_line,

			single_line, single_line);

		mutex_lock(&fl->map_mutex);

		hlist_for_each_entry_safe(map, n, &fl->maps, hn) {

			len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

				"0x%-20lX|0x%-20llX|0x%-20zu\n\n",

				map->va, map->phys,

				map->size);

		}

		mutex_unlock(&fl->map_mutex);

		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"%-20s|%-20s|%-20s|%-20s\n",

			"len", "refs",
@@ -3908,24 +3914,27 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, 
			"%s%s%s%s%s\n",

			single_line, single_line, single_line,

			single_line, single_line);

		mutex_lock(&fl->map_mutex);

		hlist_for_each_entry_safe(map, n, &fl->maps, hn) {

			len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

				"%-20zu|%-20d|0x%-20lX|%-20d\n\n",

				map->len, map->refs, map->raddr,

				map->uncached);

		}

		mutex_unlock(&fl->map_mutex);

		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"%-20s|%-20s\n", "secure", "attr");

		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"%s%s%s%s%s\n",

			single_line, single_line, single_line,

			single_line, single_line);

		mutex_lock(&fl->map_mutex);

		hlist_for_each_entry_safe(map, n, &fl->maps, hn) {

			len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

				"%-20d|0x%-20lX\n\n",

				map->secure, map->attr);

		}



		mutex_unlock(&fl->map_mutex);

		len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len,

			"\n======%s %s %s======\n", title,

			" LIST OF BUFS ", title);

drivers/clk/qcom/clk-alpha-pll.c

+7 −1
Original line number Diff line number Diff line
@@ -2310,7 +2310,13 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, 
	/* Wait for 2 reference cycles before checking the ACK bit. */

	udelay(1);

	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);

	if (!(regval & ALPHA_PLL_ACK_LATCH)) {

	if (!(regval & PLL_UPDATE_BYPASS)) {

		ret = wait_for_pll_update(pll);

		if (ret)

			WARN_CLK(hw->core, clk_hw_get_name(hw), 1,

				"PLL Update clear failed\n");

		return ret;

	} else if (!(regval & ALPHA_PLL_ACK_LATCH)) {

		WARN_CLK(hw->core, clk_hw_get_name(hw), 1,

				"PLL latch failed. Output may be unstable!\n");

		return -EINVAL;

drivers/clk/qcom/gpucc-khaje.c

+15 −12
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <linux/clk-provider.h>
@@ -24,7 +25,7 @@ 
#define CX_GMU_CBCR_WAKE_MASK		0xf

#define CX_GMU_CBCR_WAKE_SHIFT		8



static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_cx, VDD_L2_HIGH_L2 + 1, 1, vdd_l2_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);



enum {
@@ -189,9 +190,9 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { 
		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 200000000},

		.num_rate_max = VDD_L2_NUM,

		.rate_max = (unsigned long[VDD_L2_NUM]) {

			[VDD_L2_LOWER] = 200000000},

	},

};
@@ -205,6 +206,7 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { 
	F(1025000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(1100000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(1114800000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(1260000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	{ }

};
@@ -221,14 +223,15 @@ static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { 
		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_cx,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 320000097,

			[VDD_LOW] = 465000000,

			[VDD_LOW_L1] = 600000000,

			[VDD_NOMINAL] = 785088000,

			[VDD_HIGH] = 1025088000,

			[VDD_HIGH_L1] = 1114800000},

		.num_rate_max = VDD_L2_NUM,

		.rate_max = (unsigned long[VDD_L2_NUM]) {

			[VDD_L2_LOWER] = 320000097,

			[VDD_L2_LOW] = 465000000,

			[VDD_L2_LOW_L1] = 600000000,

			[VDD_L2_NOMINAL] = 785088000,

			[VDD_L2_HIGH] = 1025088000,

			[VDD_L2_HIGH_L1] = 1114800000,

			[VDD_L2_HIGH_L2] = 1260000000},

	},

};

drivers/clk/qcom/vdd-level-bengal.h

+38 −10
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.

 */



#ifndef __DRIVERS_CLK_QCOM_VDD_LEVEL_H

#define __DRIVERS_CLK_QCOM_VDD_LEVEL_H



#include <linux/regulator/consumer.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>



enum vdd_levels {

	VDD_NONE,
@@ -18,20 +19,47 @@ enum vdd_levels { 
	VDD_NOMINAL,		/* NOM */

	VDD_NOMINAL_L1,		/* NOM L1 */

	VDD_HIGH,		/* TURBO */

	VDD_HIGH_L1,		/* TURBO */

	VDD_HIGH_L1,		/* TURBO_L1 */

	VDD_NUM,

};



static int vdd_corner[] = {

	[VDD_NONE]    = 0,

	[VDD_MIN]     = RPMH_REGULATOR_LEVEL_MIN_SVS,

	[VDD_LOWER]   = RPMH_REGULATOR_LEVEL_LOW_SVS,

	[VDD_LOW]     = RPMH_REGULATOR_LEVEL_SVS,

	[VDD_LOW_L1]  = RPMH_REGULATOR_LEVEL_SVS_L1,

	[VDD_NOMINAL] = RPMH_REGULATOR_LEVEL_NOM,

	[VDD_NOMINAL_L1] = RPMH_REGULATOR_LEVEL_NOM_L1,

	[VDD_HIGH]    = RPMH_REGULATOR_LEVEL_TURBO,

	[VDD_HIGH_L1]    = RPMH_REGULATOR_LEVEL_TURBO_L1,

	[VDD_MIN]     = RPM_SMD_REGULATOR_LEVEL_MIN_SVS,

	[VDD_LOWER]   = RPM_SMD_REGULATOR_LEVEL_LOW_SVS,

	[VDD_LOW]     = RPM_SMD_REGULATOR_LEVEL_SVS,

	[VDD_LOW_L1]  = RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,

	[VDD_NOMINAL] = RPM_SMD_REGULATOR_LEVEL_NOM,

	[VDD_NOMINAL_L1] = RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,

	[VDD_HIGH]    = RPM_SMD_REGULATOR_LEVEL_TURBO,

	[VDD_HIGH_L1]    = RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,

};



enum vdd_l2_levels {

	VDD_L2_NONE,

	VDD_L2_MIN,		/* MIN SVS */

	VDD_L2_LOWER,		/* SVS2 */

	VDD_L2_LOW,		/* SVS */

	VDD_L2_LOW_L1,		/* SVSL1 */

	VDD_L2_NOMINAL,		/* NOM */

	VDD_L2_NOMINAL_L1,		/* NOM L1 */

	VDD_L2_HIGH,		/* TURBO */

	VDD_L2_HIGH_L1,		/* TURBO_L1 */

	VDD_L2_HIGH_L2,		/* TURBO L2 */

	VDD_L2_NUM,

};



static int vdd_l2_corner[] = {

	[VDD_L2_NONE]    = 0,

	[VDD_L2_MIN]     = RPM_SMD_REGULATOR_LEVEL_MIN_SVS,

	[VDD_L2_LOWER]   = RPM_SMD_REGULATOR_LEVEL_LOW_SVS,

	[VDD_L2_LOW]     = RPM_SMD_REGULATOR_LEVEL_SVS,

	[VDD_L2_LOW_L1]  = RPM_SMD_REGULATOR_LEVEL_SVS_PLUS,

	[VDD_L2_NOMINAL] = RPM_SMD_REGULATOR_LEVEL_NOM,

	[VDD_L2_NOMINAL_L1] = RPM_SMD_REGULATOR_LEVEL_NOM_PLUS,

	[VDD_L2_HIGH]    = RPM_SMD_REGULATOR_LEVEL_TURBO,

	[VDD_L2_HIGH_L1]    = RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR,

	[VDD_L2_HIGH_L2]    = RPM_SMD_REGULATOR_LEVEL_SUPER_TURBO,

};



#endif

drivers/clocksource/arm_arch_timer.c

+16 −7
Original line number Diff line number Diff line
@@ -865,15 +865,24 @@ static void arch_timer_evtstrm_enable(int divider) 


static void arch_timer_configure_evtstream(void)

{

	int evt_stream_div, pos;

	int evt_stream_div, lsb;



	/*

	 * As the event stream can at most be generated at half the frequency

	 * of the counter, use half the frequency when computing the divider.

	 */

	evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;



	/*

	 * Find the closest power of two to the divisor. If the adjacent bit

	 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).

	 */

	lsb = fls(evt_stream_div) - 1;

	if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))

		lsb++;



	/* Find the closest power of two to the divisor */

	evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;

	pos = fls(evt_stream_div);

	if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))

		pos--;

	/* enable event stream */

	arch_timer_evtstrm_enable(min(pos, 15));

	arch_timer_evtstrm_enable(max(0, min(lsb, 15)));

}



static void arch_counter_set_user_access(void)