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Commit 3d7f0f9d authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge commit drm-intel-fixes into topic/ppgtt 



I need the tricky do_switch fix before I can merge the final piece of
the ppgtt enabling puzzle. Otherwise the conflict will be a real pain
to resolve since the do_switch hunk from -fixes must be placed at the
exact right place within a hunk in the next patch.

Conflicts:
	drivers/gpu/drm/i915/i915_gem_context.c
	drivers/gpu/drm/i915/i915_gem_execbuffer.c
	drivers/gpu/drm/i915/intel_display.c

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parents 4fe9adbc 6c719fac

drivers/gpu/drm/i915/i915_dma.c

+11 −9
Original line number Diff line number Diff line
@@ -83,6 +83,14 @@ void i915_update_dri1_breadcrumb(struct drm_device *dev) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	struct drm_i915_master_private *master_priv;



	/*

	 * The dri breadcrumb update races against the drm master disappearing.

	 * Instead of trying to fix this (this is by far not the only ums issue)

	 * just don't do the update in kms mode.

	 */

	if (drm_core_check_feature(dev, DRIVER_MODESET))

		return;



	if (dev->primary->master) {

		master_priv = dev->primary->master->driver_priv;

		if (master_priv->sarea_priv)
@@ -1490,16 +1498,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	spin_lock_init(&dev_priv->uncore.lock);

	spin_lock_init(&dev_priv->mm.object_stat_lock);

	mutex_init(&dev_priv->dpio_lock);

	mutex_init(&dev_priv->rps.hw_lock);

	mutex_init(&dev_priv->modeset_restore_lock);



	mutex_init(&dev_priv->pc8.lock);

	dev_priv->pc8.requirements_met = false;

	dev_priv->pc8.gpu_idle = false;

	dev_priv->pc8.irqs_disabled = false;

	dev_priv->pc8.enabled = false;

	dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */

	INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);

	intel_pm_setup(dev);



	intel_display_crc_init(dev);
@@ -1603,7 +1604,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	}



	intel_irq_init(dev);

	intel_pm_init(dev);

	intel_uncore_sanitize(dev);



	/* Try to make sure MCHBAR is enabled before poking at it */
@@ -1845,8 +1845,10 @@ void i915_driver_lastclose(struct drm_device * dev) 


void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)

{

	mutex_lock(&dev->struct_mutex);

	i915_gem_context_close(dev, file_priv);

	i915_gem_release(dev, file_priv);

	mutex_unlock(&dev->struct_mutex);

}



void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)

drivers/gpu/drm/i915/i915_drv.c

+3 −0
Original line number Diff line number Diff line
@@ -535,8 +535,10 @@ static int i915_drm_freeze(struct drm_device *dev) 
		 * Disable CRTCs directly since we want to preserve sw state

		 * for _thaw.

		 */

		mutex_lock(&dev->mode_config.mutex);

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

			dev_priv->display.crtc_disable(crtc);

		mutex_unlock(&dev->mode_config.mutex);



		intel_modeset_suspend_hw(dev);

	}
@@ -650,6 +652,7 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) 
		intel_modeset_init_hw(dev);



		drm_modeset_lock_all(dev);

		drm_mode_config_reset(dev);

		intel_modeset_setup_hw_state(dev, true);

		drm_modeset_unlock_all(dev);

drivers/gpu/drm/i915/i915_drv.h

+0 −2
Original line number Diff line number Diff line
@@ -1944,9 +1944,7 @@ void i915_queue_hangcheck(struct drm_device *dev); 
void i915_handle_error(struct drm_device *dev, bool wedged);



extern void intel_irq_init(struct drm_device *dev);

extern void intel_pm_init(struct drm_device *dev);

extern void intel_hpd_init(struct drm_device *dev);

extern void intel_pm_init(struct drm_device *dev);



extern void intel_uncore_sanitize(struct drm_device *dev);

extern void intel_uncore_early_sanitize(struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+3 −4
Original line number Diff line number Diff line
@@ -4421,10 +4421,9 @@ i915_gem_init_hw(struct drm_device *dev) 
	if (dev_priv->ellc_size)

		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));



	if (IS_HSW_GT3(dev))

		I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);

	else

		I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);

	if (IS_HASWELL(dev))

		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?

			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);



	if (HAS_PCH_NOP(dev)) {

		u32 temp = I915_READ(GEN7_MSG_CTL);

drivers/gpu/drm/i915/i915_gem_context.c

+12 −4
Original line number Diff line number Diff line
@@ -520,11 +520,9 @@ void i915_gem_context_close(struct drm_device *dev, struct drm_file *file) 
		return;

	}



	mutex_lock(&dev->struct_mutex);

	idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);

	i915_gem_context_unreference(file_priv->private_default_ctx);

	idr_destroy(&file_priv->context_idr);

	mutex_unlock(&dev->struct_mutex);

}



struct i915_hw_context *
@@ -611,11 +609,21 @@ static int do_switch(struct intel_ring_buffer *ring, 
	if (ret)

		return ret;



	/* Clear this page out of any CPU caches for coherent swap-in/out. Note

	/*

	 * Pin can switch back to the default context if we end up calling into

	 * evict_everything - as a last ditch gtt defrag effort that also

	 * switches to the default context. Hence we need to reload from here.

	 */

	from = ring->last_context;



	/*

	 * Clear this page out of any CPU caches for coherent swap-in/out. Note

	 * that thanks to write = false in this call and us not setting any gpu

	 * write domains when putting a context object onto the active list

	 * (when switching away from it), this won't block.

	 * XXX: We need a real interface to do this instead of trickery. */

	 *

	 * XXX: We need a real interface to do this instead of trickery.

	 */

	ret = i915_gem_object_set_to_gtt_domain(to->obj, false);

	if (ret) {

		i915_gem_object_ggtt_unpin(to->obj);