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Commit 3d3cacc0 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'mvebu-soc-4.3-2' of git://git.infradead.org/linux-mvebu into next/drivers 

mvebu soc changes for v4.3 (part #2)

SoC part of the Dove PMU series

* tag 'mvebu-soc-4.3-2' of git://git.infradead.org/linux-mvebu

:
  ARM: dove: create a proper PMU driver for power domains, PMU IRQs and resets

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 0ff818ef 44e259ac

arch/arm/mach-mvebu/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ config MACH_DOVE 
	select MACH_MVEBU_ANY

	select ORION_IRQCHIP

	select ORION_TIMER

	select PM_GENERIC_DOMAINS if PM

	select PINCTRL_DOVE

	help

	  Say 'Y' here if you want your kernel to support the

arch/arm/mach-mvebu/coherency.c

+17 −12
Original line number Diff line number Diff line
@@ -65,18 +65,6 @@ static const struct of_device_id of_coherency_table[] = { 
int ll_enable_coherency(void);

void ll_add_cpu_to_smp_group(void);



int set_cpu_coherent(void)

{

	if (!coherency_base) {

		pr_warn("Can't make current CPU cache coherent.\n");

		pr_warn("Coherency fabric is not initialized\n");

		return 1;

	}



	ll_add_cpu_to_smp_group();

	return ll_enable_coherency();

}



static int mvebu_hwcc_notifier(struct notifier_block *nb,

			       unsigned long event, void *__dev)

{
@@ -206,6 +194,23 @@ static int coherency_type(void) 
	return type;

}



int set_cpu_coherent(void)

{

	int type = coherency_type();



	if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {

		if (!coherency_base) {

			pr_warn("Can't make current CPU cache coherent.\n");

			pr_warn("Coherency fabric is not initialized\n");

			return 1;

		}

		ll_add_cpu_to_smp_group();

		return ll_enable_coherency();

	}



	return 0;

}



int coherency_available(void)

{

	return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;

arch/arm/mach-mvebu/common.h

+2 −2
Original line number Diff line number Diff line
@@ -25,6 +25,6 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev); 


void __iomem *mvebu_get_scu_base(void);



int mvebu_pm_init(void (*board_pm_enter)(void __iomem *sdram_reg, u32 srcmd));



int mvebu_pm_suspend_init(void (*board_pm_enter)(void __iomem *sdram_reg,

							u32 srcmd));

#endif

arch/arm/mach-mvebu/dove.c

+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/mbus.h>

#include <linux/of.h>

#include <linux/of_platform.h>

#include <linux/soc/dove/pmu.h>

#include <asm/hardware/cache-tauros2.h>

#include <asm/mach/arch.h>

#include "common.h"
@@ -24,6 +25,7 @@ static void __init dove_init(void) 
	tauros2_init(0);

#endif

	BUG_ON(mvebu_mbus_dt_init(false));

	dove_init_pmu();

	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);

}

arch/arm/mach-mvebu/pm-board.c

+19 −11
Original line number Diff line number Diff line 
/*

 * Board-level suspend/resume support.

 *

 * Copyright (C) 2014 Marvell

 * Copyright (C) 2014-2015 Marvell

 *

 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

 *
@@ -20,27 +20,27 @@ 
#include <linux/slab.h>

#include "common.h"



#define ARMADA_XP_GP_PIC_NR_GPIOS 3

#define ARMADA_PIC_NR_GPIOS 3



static void __iomem *gpio_ctrl;

static int pic_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];

static int pic_raw_gpios[ARMADA_XP_GP_PIC_NR_GPIOS];

static int pic_gpios[ARMADA_PIC_NR_GPIOS];

static int pic_raw_gpios[ARMADA_PIC_NR_GPIOS];



static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)

static void mvebu_armada_pm_enter(void __iomem *sdram_reg, u32 srcmd)

{

	u32 reg, ackcmd;

	int i;



	/* Put 001 as value on the GPIOs */

	reg = readl(gpio_ctrl);

	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)

	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)

		reg &= ~BIT(pic_raw_gpios[i]);

	reg |= BIT(pic_raw_gpios[0]);

	writel(reg, gpio_ctrl);



	/* Prepare writing 111 to the GPIOs */

	ackcmd = readl(gpio_ctrl);

	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)

	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++)

		ackcmd |= BIT(pic_raw_gpios[i]);



	srcmd = cpu_to_le32(srcmd);
@@ -76,7 +76,7 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd) 
		  [ackcmd] "r" (ackcmd), [gpio_ctrl] "r" (gpio_ctrl) : "r1");

}



static int mvebu_armada_xp_gp_pm_init(void)

static int __init mvebu_armada_pm_init(void)

{

	struct device_node *np;

	struct device_node *gpio_ctrl_np;
@@ -89,7 +89,7 @@ static int mvebu_armada_xp_gp_pm_init(void) 
	if (!np)

		return -ENODEV;



	for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++) {

	for (i = 0; i < ARMADA_PIC_NR_GPIOS; i++) {

		char *name;

		struct of_phandle_args args;
@@ -134,11 +134,19 @@ static int mvebu_armada_xp_gp_pm_init(void) 
	if (!gpio_ctrl)

		return -ENOMEM;



	mvebu_pm_init(mvebu_armada_xp_gp_pm_enter);

	mvebu_pm_suspend_init(mvebu_armada_pm_enter);



out:

	of_node_put(np);

	return ret;

}



late_initcall(mvebu_armada_xp_gp_pm_init);
 
/*

 * Registering the mvebu_board_pm_enter callback must be done before

 * the platform_suspend_ops will be registered. In the same time we

 * also need to have the gpio devices registered. That's why we use a

 * device_initcall_sync which is called after all the device_initcall

 * (used by the gpio device) but before the late_initcall (used to

 * register the platform_suspend_ops)

 */

device_initcall_sync(mvebu_armada_pm_init);