Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3d2e8701 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU 



CCI-550 PMU shares most of the CCI-500 PMU attributes including the
event format, PMU event codes. The only difference is an additional
master interface (MI6 - 0xe). Hence we share the driver code for both,
except for a model specific event validate method.
This patch renames the common CCI500 symbols to CCI5xx, including the
Kconfig symbol.

No functional changes to the PMU driver.

Acked-by: default avatarOlof Johansson <olof@lixom.net>
Acked-by: default avatarPunit Agrawal <punit.agrawal@arm.com>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent a445fcc9

drivers/bus/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ config ARM_CCI400_PORT_CTRL 
	  Low level power management driver for CCI400 cache coherent

	  interconnect for ARM platforms.



config ARM_CCI500_PMU

config ARM_CCI5xx_PMU

	bool "ARM CCI500 PMU support"

	depends on (ARM && CPU_V7) || ARM64

	depends on PERF_EVENTS

drivers/bus/arm-cci.c

+112 −108
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static const struct of_device_id arm_cci_matches[] = { 
#ifdef CONFIG_ARM_CCI400_COMMON

	{.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },

#endif

#ifdef CONFIG_ARM_CCI500_PMU

#ifdef CONFIG_ARM_CCI5xx_PMU

	{ .compatible = "arm,cci-500", },

#endif

	{},
@@ -92,7 +92,7 @@ static const struct of_device_id arm_cci_matches[] = { 
enum {

	CCI_IF_SLAVE,

	CCI_IF_MASTER,

#ifdef CONFIG_ARM_CCI500_PMU

#ifdef CONFIG_ARM_CCI5xx_PMU

	CCI_IF_GLOBAL,

#endif

	CCI_IF_MAX,
@@ -154,7 +154,7 @@ enum cci_models { 
	CCI400_R0,

	CCI400_R1,

#endif

#ifdef CONFIG_ARM_CCI500_PMU

#ifdef CONFIG_ARM_CCI5xx_PMU

	CCI500_R0,

#endif

	CCI_MODEL_MAX
@@ -426,73 +426,67 @@ static inline struct cci_pmu_model *probe_cci_model(struct platform_device *pdev 
}

#endif	/* CONFIG_ARM_CCI400_PMU */



#ifdef CONFIG_ARM_CCI500_PMU

#ifdef CONFIG_ARM_CCI5xx_PMU



/*

 * CCI500 provides 8 independent event counters that can count

 * any of the events available.

 *

 * CCI500 PMU event id is an 9-bit value made of two parts.

 * CCI5xx PMU event id is an 9-bit value made of two parts.

 *	 bits [8:5] - Source for the event

 *		      0x0-0x6 - Slave interfaces

 *		      0x8-0xD - Master interfaces

 *		      0xf     - Global Events

 *		      0x7,0xe - Reserved

 *

 *	 bits [4:0] - Event code (specific to type of interface)

 *

 *

 */



/* Port ids */

#define CCI500_PORT_S0			0x0

#define CCI500_PORT_S1			0x1

#define CCI500_PORT_S2			0x2

#define CCI500_PORT_S3			0x3

#define CCI500_PORT_S4			0x4

#define CCI500_PORT_S5			0x5

#define CCI500_PORT_S6			0x6



#define CCI500_PORT_M0			0x8

#define CCI500_PORT_M1			0x9

#define CCI500_PORT_M2			0xa

#define CCI500_PORT_M3			0xb

#define CCI500_PORT_M4			0xc

#define CCI500_PORT_M5			0xd



#define CCI500_PORT_GLOBAL 		0xf



#define CCI500_PMU_EVENT_MASK		0x1ffUL

#define CCI500_PMU_EVENT_SOURCE_SHIFT	0x5

#define CCI500_PMU_EVENT_SOURCE_MASK	0xf

#define CCI500_PMU_EVENT_CODE_SHIFT	0x0

#define CCI500_PMU_EVENT_CODE_MASK	0x1f



#define CCI500_PMU_EVENT_SOURCE(event)	\

	((event >> CCI500_PMU_EVENT_SOURCE_SHIFT) & CCI500_PMU_EVENT_SOURCE_MASK)

#define CCI500_PMU_EVENT_CODE(event)	\

	((event >> CCI500_PMU_EVENT_CODE_SHIFT) & CCI500_PMU_EVENT_CODE_MASK)



#define CCI500_SLAVE_PORT_MIN_EV	0x00

#define CCI500_SLAVE_PORT_MAX_EV	0x1f

#define CCI500_MASTER_PORT_MIN_EV	0x00

#define CCI500_MASTER_PORT_MAX_EV	0x06

#define CCI500_GLOBAL_PORT_MIN_EV	0x00

#define CCI500_GLOBAL_PORT_MAX_EV	0x0f





#define CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(_name, _config) \

	CCI_EXT_ATTR_ENTRY(_name, cci500_pmu_global_event_show, \

#define CCI5xx_PORT_S0			0x0

#define CCI5xx_PORT_S1			0x1

#define CCI5xx_PORT_S2			0x2

#define CCI5xx_PORT_S3			0x3

#define CCI5xx_PORT_S4			0x4

#define CCI5xx_PORT_S5			0x5

#define CCI5xx_PORT_S6			0x6



#define CCI5xx_PORT_M0			0x8

#define CCI5xx_PORT_M1			0x9

#define CCI5xx_PORT_M2			0xa

#define CCI5xx_PORT_M3			0xb

#define CCI5xx_PORT_M4			0xc

#define CCI5xx_PORT_M5			0xd



#define CCI5xx_PORT_GLOBAL		0xf



#define CCI5xx_PMU_EVENT_MASK		0x1ffUL

#define CCI5xx_PMU_EVENT_SOURCE_SHIFT	0x5

#define CCI5xx_PMU_EVENT_SOURCE_MASK	0xf

#define CCI5xx_PMU_EVENT_CODE_SHIFT	0x0

#define CCI5xx_PMU_EVENT_CODE_MASK	0x1f



#define CCI5xx_PMU_EVENT_SOURCE(event)	\

	((event >> CCI5xx_PMU_EVENT_SOURCE_SHIFT) & CCI5xx_PMU_EVENT_SOURCE_MASK)

#define CCI5xx_PMU_EVENT_CODE(event)	\

	((event >> CCI5xx_PMU_EVENT_CODE_SHIFT) & CCI5xx_PMU_EVENT_CODE_MASK)



#define CCI5xx_SLAVE_PORT_MIN_EV	0x00

#define CCI5xx_SLAVE_PORT_MAX_EV	0x1f

#define CCI5xx_MASTER_PORT_MIN_EV	0x00

#define CCI5xx_MASTER_PORT_MAX_EV	0x06

#define CCI5xx_GLOBAL_PORT_MIN_EV	0x00

#define CCI5xx_GLOBAL_PORT_MAX_EV	0x0f





#define CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(_name, _config) \

	CCI_EXT_ATTR_ENTRY(_name, cci5xx_pmu_global_event_show, \

					(unsigned long) _config)



static ssize_t cci500_pmu_global_event_show(struct device *dev,

static ssize_t cci5xx_pmu_global_event_show(struct device *dev,

				struct device_attribute *attr, char *buf);



static struct attribute *cci500_pmu_format_attrs[] = {

static struct attribute *cci5xx_pmu_format_attrs[] = {

	CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),

	CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-8"),

	NULL,

};



static struct attribute *cci500_pmu_event_attrs[] = {

static struct attribute *cci5xx_pmu_event_attrs[] = {

	/* Slave events */

	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_arvalid, 0x0),

	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_dev, 0x1),
@@ -537,64 +531,73 @@ static struct attribute *cci500_pmu_event_attrs[] = { 
	CCI_EVENT_EXT_ATTR_ENTRY(mi_w_resp_stall, 0x6),



	/* Global events */

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_0_1, 0x0),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_2_3, 0x1),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_4_5, 0x2),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_6_7, 0x3),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_0_1, 0x4),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_2_3, 0x5),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_4_5, 0x6),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_6_7, 0x7),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_back_invalidation, 0x8),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_alloc_busy, 0x9),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_tt_full, 0xA),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_wrq, 0xB),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_cd_hs, 0xC),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_rq_stall_addr_hazard, 0xD),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snopp_rq_stall_tt_full, 0xE),

	CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_tzmp1_prot, 0xF),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_0_1, 0x0),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_2_3, 0x1),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_4_5, 0x2),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_6_7, 0x3),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_0_1, 0x4),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_2_3, 0x5),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_4_5, 0x6),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_6_7, 0x7),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_back_invalidation, 0x8),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_alloc_busy, 0x9),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_tt_full, 0xA),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_wrq, 0xB),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_cd_hs, 0xC),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_rq_stall_addr_hazard, 0xD),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snopp_rq_stall_tt_full, 0xE),

	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_tzmp1_prot, 0xF),

	NULL

};



static ssize_t cci500_pmu_global_event_show(struct device *dev,

static ssize_t cci5xx_pmu_global_event_show(struct device *dev,

				struct device_attribute *attr, char *buf)

{

	struct dev_ext_attribute *eattr = container_of(attr,

					struct dev_ext_attribute, attr);

	/* Global events have single fixed source code */

	return snprintf(buf, PAGE_SIZE, "event=0x%lx,source=0x%x\n",

				(unsigned long)eattr->var, CCI500_PORT_GLOBAL);

				(unsigned long)eattr->var, CCI5xx_PORT_GLOBAL);

}



/*

 * CCI500 provides 8 independent event counters that can count

 * any of the events available.

 * CCI500 PMU event source ids

 *	0x0-0x6 - Slave interfaces

 *	0x8-0xD - Master interfaces

 *	0xf     - Global Events

 *	0x7,0xe - Reserved

 */

static int cci500_validate_hw_event(struct cci_pmu *cci_pmu,

					unsigned long hw_event)

{

	u32 ev_source = CCI500_PMU_EVENT_SOURCE(hw_event);

	u32 ev_code = CCI500_PMU_EVENT_CODE(hw_event);

	u32 ev_source = CCI5xx_PMU_EVENT_SOURCE(hw_event);

	u32 ev_code = CCI5xx_PMU_EVENT_CODE(hw_event);

	int if_type;



	if (hw_event & ~CCI500_PMU_EVENT_MASK)

	if (hw_event & ~CCI5xx_PMU_EVENT_MASK)

		return -ENOENT;



	switch (ev_source) {

	case CCI500_PORT_S0:

	case CCI500_PORT_S1:

	case CCI500_PORT_S2:

	case CCI500_PORT_S3:

	case CCI500_PORT_S4:

	case CCI500_PORT_S5:

	case CCI500_PORT_S6:

	case CCI5xx_PORT_S0:

	case CCI5xx_PORT_S1:

	case CCI5xx_PORT_S2:

	case CCI5xx_PORT_S3:

	case CCI5xx_PORT_S4:

	case CCI5xx_PORT_S5:

	case CCI5xx_PORT_S6:

		if_type = CCI_IF_SLAVE;

		break;

	case CCI500_PORT_M0:

	case CCI500_PORT_M1:

	case CCI500_PORT_M2:

	case CCI500_PORT_M3:

	case CCI500_PORT_M4:

	case CCI500_PORT_M5:

	case CCI5xx_PORT_M0:

	case CCI5xx_PORT_M1:

	case CCI5xx_PORT_M2:

	case CCI5xx_PORT_M3:

	case CCI5xx_PORT_M4:

	case CCI5xx_PORT_M5:

		if_type = CCI_IF_MASTER;

		break;

	case CCI500_PORT_GLOBAL:

	case CCI5xx_PORT_GLOBAL:

		if_type = CCI_IF_GLOBAL;

		break;

	default:
@@ -607,7 +610,8 @@ static int cci500_validate_hw_event(struct cci_pmu *cci_pmu, 


	return -ENOENT;

}

#endif	/* CONFIG_ARM_CCI500_PMU */



#endif	/* CONFIG_ARM_CCI5xx_PMU */



/*

 * Program the CCI PMU counters which have PERF_HES_ARCH set
@@ -891,7 +895,7 @@ static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask) 
		__pmu_write_counters(cci_pmu, mask);

}



#ifdef CONFIG_ARM_CCI500_PMU

#ifdef CONFIG_ARM_CCI5xx_PMU



/*

 * CCI-500 has advanced power saving policies, which could gate the
@@ -917,12 +921,12 @@ static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask) 
 * 8) Disable the global PMU.

 * 9) Restore the status of the rest of the counters.

 *

 * We choose an event which for CCI-500 is guaranteed not to count.

 * We choose an event which for CCI-5xx is guaranteed not to count.

 * We use the highest possible event code (0x1f) for the master interface 0.

 */

#define CCI500_INVALID_EVENT	((CCI500_PORT_M0 << CCI500_PMU_EVENT_SOURCE_SHIFT) | \

				 (CCI500_PMU_EVENT_CODE_MASK << CCI500_PMU_EVENT_CODE_SHIFT))

static void cci500_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)

#define CCI5xx_INVALID_EVENT	((CCI5xx_PORT_M0 << CCI5xx_PMU_EVENT_SOURCE_SHIFT) | \

				 (CCI5xx_PMU_EVENT_CODE_MASK << CCI5xx_PMU_EVENT_CODE_SHIFT))

static void cci5xx_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)

{

	int i;

	DECLARE_BITMAP(saved_mask, cci_pmu->num_cntrs);
@@ -942,7 +946,7 @@ static void cci500_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *ma 
		if (WARN_ON(!event))

			continue;



		pmu_set_event(cci_pmu, i, CCI500_INVALID_EVENT);

		pmu_set_event(cci_pmu, i, CCI5xx_INVALID_EVENT);

		pmu_enable_counter(cci_pmu, i);

		pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i);

		pmu_disable_counter(cci_pmu, i);
@@ -954,7 +958,7 @@ static void cci500_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *ma 
	pmu_restore_counters(cci_pmu, saved_mask);

}



#endif	/* CONFIG_ARM_CCI500_PMU */

#endif	/* CONFIG_ARM_CCI5xx_PMU */



static u64 pmu_event_update(struct perf_event *event)

{
@@ -1517,30 +1521,30 @@ static struct cci_pmu_model cci_pmu_models[] = { 
		.get_event_idx = cci400_get_event_idx,

	},

#endif

#ifdef CONFIG_ARM_CCI500_PMU

#ifdef CONFIG_ARM_CCI5xx_PMU

	[CCI500_R0] = {

		.name = "CCI_500",

		.fixed_hw_cntrs = 0,

		.num_hw_cntrs = 8,

		.cntr_size = SZ_64K,

		.format_attrs = cci500_pmu_format_attrs,

		.event_attrs = cci500_pmu_event_attrs,

		.format_attrs = cci5xx_pmu_format_attrs,

		.event_attrs = cci5xx_pmu_event_attrs,

		.event_ranges = {

			[CCI_IF_SLAVE] = {

				CCI500_SLAVE_PORT_MIN_EV,

				CCI500_SLAVE_PORT_MAX_EV,

				CCI5xx_SLAVE_PORT_MIN_EV,

				CCI5xx_SLAVE_PORT_MAX_EV,

			},

			[CCI_IF_MASTER] = {

				CCI500_MASTER_PORT_MIN_EV,

				CCI500_MASTER_PORT_MAX_EV,

				CCI5xx_MASTER_PORT_MIN_EV,

				CCI5xx_MASTER_PORT_MAX_EV,

			},

			[CCI_IF_GLOBAL] = {

				CCI500_GLOBAL_PORT_MIN_EV,

				CCI500_GLOBAL_PORT_MAX_EV,

				CCI5xx_GLOBAL_PORT_MIN_EV,

				CCI5xx_GLOBAL_PORT_MAX_EV,

			},

		},

		.validate_hw_event = cci500_validate_hw_event,

		.write_counters	= cci500_pmu_write_counters,

		.write_counters	= cci5xx_pmu_write_counters,

	},

#endif

};
@@ -1560,7 +1564,7 @@ static const struct of_device_id arm_cci_pmu_matches[] = { 
		.data	= &cci_pmu_models[CCI400_R1],

	},

#endif

#ifdef CONFIG_ARM_CCI500_PMU

#ifdef CONFIG_ARM_CCI5xx_PMU

	{

		.compatible = "arm,cci-500-pmu,r0",

		.data = &cci_pmu_models[CCI500_R0],