Merge remote branch 'kumar/next' into next

CAN Device Tree Bindings

------------------------

2011 Freescale Semiconductor, Inc.

fsl,flexcan-v1.0 nodes

-----------------------

In addition to the required compatible-, reg- and interrupt-properties, you can

also specify which clock source shall be used for the controller.

CPI Clock- Can Protocol Interface Clock

	This CLK_SRC bit of CTRL(control register) selects the clock source to

	the CAN Protocol Interface(CPI) to be either the peripheral clock

	(driven by the PLL) or the crystal oscillator clock. The selected clock

	is the one fed to the prescaler to generate the Serial Clock (Sclock).

	The PRESDIV field of CTRL(control register) controls a prescaler that

	generates the Serial Clock (Sclock), whose period defines the

	time quantum used to compose the CAN waveform.

Can Engine Clock Source

	There are two sources for CAN clock

	- Platform Clock  It represents the bus clock

	- Oscillator Clock

	Peripheral Clock (PLL)

	--------------

		     |

		    ---------		      -------------

		    |       |CPI Clock	      | Prescaler |       Sclock

		    |       |---------------->| (1.. 256) |------------>

		    ---------		      -------------

                     |  |

	--------------  ---------------------CLK_SRC

	Oscillator Clock

- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects

			     the peripheral clock. PLL clock is fed to the

			     prescaler to generate the Serial Clock (Sclock).

			     Valid values are "oscillator" and "platform"

			     "oscillator": CAN engine clock source is oscillator clock.

			     "platform" The CAN engine clock source is the bus clock

		             (platform clock).

- fsl,flexcan-clock-divider : for the reference and system clock, an additional

			      clock divider can be specified.

- clock-frequency: frequency required to calculate the bitrate for FlexCAN.

Note:

	- v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.

	- P1010 does not have oscillator as the Clock Source.So the default

	  Clock Source is platform clock.

Examples:

	can0@1c000 {

		compatible = "fsl,flexcan-v1.0";

		reg = <0x1c000 0x1000>;

		interrupts = <48 0x2>;

		interrupt-parent = <&mpic>;

		fsl,flexcan-clock-source = "platform";

		fsl,flexcan-clock-divider = <2>;

		clock-frequency = <fixed by u-boot>;

	};

Integrated Flash Controller

Properties:

- name : Should be ifc

- compatible : should contain "fsl,ifc". The version of the integrated

               flash controller can be found in the IFC_REV register at

               offset zero.

- #address-cells : Should be either two or three.  The first cell is the

                   chipselect number, and the remaining cells are the

                   offset into the chipselect.

- #size-cells : Either one or two, depending on how large each chipselect

                can be.

- reg : Offset and length of the register set for the device

- interrupts : IFC has two interrupts. The first one is the "common"

               interrupt(CM_EVTER_STAT), and second is the NAND interrupt

               (NAND_EVTER_STAT).

- ranges : Each range corresponds to a single chipselect, and covers

           the entire access window as configured.

Child device nodes describe the devices connected to IFC such as NOR (e.g.

cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices

like FPGAs, CPLDs, etc.

Example:

	ifc@ffe1e000 {

		compatible = "fsl,ifc", "simple-bus";

		#address-cells = <2>;

		#size-cells = <1>;

		reg = <0x0 0xffe1e000 0 0x2000>;

		interrupts = <16 2 19 2>;

		/* NOR, NAND Flashes and CPLD on board */

		ranges = <0x0 0x0 0x0 0xee000000 0x02000000

			  0x1 0x0 0x0 0xffa00000 0x00010000

			  0x3 0x0 0x0 0xffb00000 0x00020000>;

		flash@0,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "cfi-flash";

			reg = <0x0 0x0 0x2000000>;

			bank-width = <2>;

			device-width = <1>;

			partition@0 {

				/* 32MB for user data */

				reg = <0x0 0x02000000>;

				label = "NOR Data";

			};

		};

		flash@1,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,ifc-nand";

			reg = <0x1 0x0 0x10000>;

			partition@0 {

				/* This location must not be altered  */

				/* 1MB for u-boot Bootloader Image */

				reg = <0x0 0x00100000>;

				label = "NAND U-Boot Image";

				read-only;

			};

		};

		cpld@3,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,p1010rdb-cpld";

			reg = <0x3 0x0 0x000001f>;

		};

	};

* Freescale MPIC timers

Required properties:

- compatible: "fsl,mpic-global-timer"

- reg : Contains two regions.  The first is the main timer register bank

  (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx).  The second is the timer control

  register (TCRx) for the group.

- fsl,available-ranges: use <start count> style section to define which

  timer interrupts can be used.  This property is optional; without this,

  all timers within the group can be used.

- interrupts: one interrupt per timer in the group, in order, starting

  with timer zero.  If timer-available-ranges is present, only the

  interrupts that correspond to available timers shall be present.

Example:

	/* Note that this requires #interrupt-cells to be 4 */

	timer0: timer@41100 {

		compatible = "fsl,mpic-global-timer";

		reg = <0x41100 0x100 0x41300 4>;

		/* Another AMP partition is using timers 0 and 1 */

		fsl,available-ranges = <2 2>;

		interrupts = <2 0 3 0

		              3 0 3 0>;

	};

	timer1: timer@42100 {

		compatible = "fsl,mpic-global-timer";

		reg = <0x42100 0x100 0x42300 4>;

		interrupts = <4 0 3 0

		              5 0 3 0

		              6 0 3 0

		              7 0 3 0>;

	};

	 */

	 */

	timer0: timer@41100 {

	timer0: timer@41100 {

		compatible = "fsl,mpic-global-timer";

		compatible = "fsl,mpic-global-timer";

		reg = <0x41100 0x100>;

		reg = <0x41100 0x100 0x41300 4>;

		interrupts = <0 0 3 0

		interrupts = <0 0 3 0

		              1 0 3 0

		              1 0 3 0

		              2 0 3 0

		              2 0 3 0

 * option) any later version.

 * option) any later version.

 */

 */

/dts-v1/;

/include/ "p1020si.dtsi"

/ {

/ {

	model = "fsl,P1020";

	model = "fsl,P1020RDB";

	compatible = "fsl,P1020RDB";

	compatible = "fsl,P1020RDB";

	#address-cells = <2>;

	#size-cells = <2>;

	aliases {

	aliases {

		serial0 = &serial0;

		serial0 = &serial0;

		pci1 = &pci1;

		pci1 = &pci1;

	};

	};

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		PowerPC,P1020@0 {

			device_type = "cpu";

			reg = <0x0>;

			next-level-cache = <&L2>;

		};

		PowerPC,P1020@1 {

			device_type = "cpu";

			reg = <0x1>;

			next-level-cache = <&L2>;

		};

	};

	memory {

	memory {

		device_type = "memory";

		device_type = "memory";

	};

	};

	localbus@ffe05000 {

	localbus@ffe05000 {

		#address-cells = <2>;

		#size-cells = <1>;

		compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";

		reg = <0 0xffe05000 0 0x1000>;

		interrupts = <19 2>;

		interrupt-parent = <&mpic>;

		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */

		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */

		ranges = <0x0 0x0 0x0 0xef000000 0x01000000

		ranges = <0x0 0x0 0x0 0xef000000 0x01000000

	};

	};

	soc@ffe00000 {

	soc@ffe00000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		compatible = "fsl,p1020-immr", "simple-bus";

		ranges = <0x0  0x0 0xffe00000 0x100000>;

		bus-frequency = <0>;		// Filled out by uboot.

		ecm-law@0 {

			compatible = "fsl,ecm-law";

			reg = <0x0 0x1000>;

			fsl,num-laws = <12>;

		};

		ecm@1000 {

			compatible = "fsl,p1020-ecm", "fsl,ecm";

			reg = <0x1000 0x1000>;

			interrupts = <16 2>;

			interrupt-parent = <&mpic>;

		};

		memory-controller@2000 {

			compatible = "fsl,p1020-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <16 2>;

		};

		i2c@3000 {

		i2c@3000 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <0x3000 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

			rtc@68 {

			rtc@68 {

				compatible = "dallas,ds1339";

				compatible = "dallas,ds1339";

				reg = <0x68>;

				reg = <0x68>;

			};

			};

		};

		};

		i2c@3100 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <1>;

			compatible = "fsl-i2c";

			reg = <0x3100 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};

		serial0: serial@4500 {

			cell-index = <0>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <0x4500 0x100>;

			clock-frequency = <0>;

			interrupts = <42 2>;

			interrupt-parent = <&mpic>;

		};

		serial1: serial@4600 {

			cell-index = <1>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <0x4600 0x100>;

			clock-frequency = <0>;

			interrupts = <42 2>;

			interrupt-parent = <&mpic>;

		};

		spi@7000 {

		spi@7000 {

			cell-index = <0>;

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,espi";

			reg = <0x7000 0x1000>;

			interrupts = <59 0x2>;

			interrupt-parent = <&mpic>;

			mode = "cpu";

			fsl_m25p80@0 {

			fsl_m25p80@0 {

				#address-cells = <1>;

				#address-cells = <1>;

			};

			};

		};

		};

		gpio: gpio-controller@f000 {

			#gpio-cells = <2>;

			compatible = "fsl,mpc8572-gpio";

			reg = <0xf000 0x100>;

			interrupts = <47 0x2>;

			interrupt-parent = <&mpic>;

			gpio-controller;

		};

		L2: l2-cache-controller@20000 {

			compatible = "fsl,p1020-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x40000>; // L2,256K

			interrupt-parent = <&mpic>;

			interrupts = <16 2>;

		};

		dma@21300 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,eloplus-dma";

			reg = <0x21300 0x4>;

			ranges = <0x0 0x21100 0x200>;

			cell-index = <0>;

			dma-channel@0 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x0 0x80>;

				cell-index = <0>;

				interrupt-parent = <&mpic>;

				interrupts = <20 2>;

			};

			dma-channel@80 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x80 0x80>;

				cell-index = <1>;

				interrupt-parent = <&mpic>;

				interrupts = <21 2>;

			};

			dma-channel@100 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x100 0x80>;

				cell-index = <2>;

				interrupt-parent = <&mpic>;

				interrupts = <22 2>;

			};

			dma-channel@180 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x180 0x80>;

				cell-index = <3>;

				interrupt-parent = <&mpic>;

				interrupts = <23 2>;

			};

		};

		mdio@24000 {

		mdio@24000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,etsec2-mdio";

			reg = <0x24000 0x1000 0xb0030 0x4>;

			phy0: ethernet-phy@0 {

			phy0: ethernet-phy@0 {

				interrupt-parent = <&mpic>;

				interrupt-parent = <&mpic>;

		};

		};

		mdio@25000 {

		mdio@25000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,etsec2-tbi";

			reg = <0x25000 0x1000 0xb1030 0x4>;

			tbi0: tbi-phy@11 {

			tbi0: tbi-phy@11 {

				reg = <0x11>;

				reg = <0x11>;

		};

		};

		enet0: ethernet@b0000 {

		enet0: ethernet@b0000 {

			#address-cells = <1>;

			#size-cells = <1>;

			device_type = "network";

			model = "eTSEC";

			compatible = "fsl,etsec2";

			fsl,num_rx_queues = <0x8>;

			fsl,num_tx_queues = <0x8>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupt-parent = <&mpic>;

			fixed-link = <1 1 1000 0 0>;

			fixed-link = <1 1 1000 0 0>;

			phy-connection-type = "rgmii-id";

			phy-connection-type = "rgmii-id";

			queue-group@0 {

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0xb0000 0x1000>;

				interrupts = <29 2 30 2 34 2>;

			};

			queue-group@1 {

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0xb4000 0x1000>;

				interrupts = <17 2 18 2 24 2>;

			};

		};

		};

		enet1: ethernet@b1000 {

		enet1: ethernet@b1000 {

			#address-cells = <1>;

			#size-cells = <1>;

			device_type = "network";

			model = "eTSEC";

			compatible = "fsl,etsec2";

			fsl,num_rx_queues = <0x8>;

			fsl,num_tx_queues = <0x8>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupt-parent = <&mpic>;

			phy-handle = <&phy0>;

			phy-handle = <&phy0>;

			tbi-handle = <&tbi0>;

			tbi-handle = <&tbi0>;

			phy-connection-type = "sgmii";

			phy-connection-type = "sgmii";

			queue-group@0 {

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0xb1000 0x1000>;

				interrupts = <35 2 36 2 40 2>;

			};

			queue-group@1 {

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0xb5000 0x1000>;

				interrupts = <51 2 52 2 67 2>;

			};

		};

		};

		enet2: ethernet@b2000 {

		enet2: ethernet@b2000 {

			#address-cells = <1>;

			#size-cells = <1>;

			device_type = "network";

			model = "eTSEC";

			compatible = "fsl,etsec2";

			fsl,num_rx_queues = <0x8>;

			fsl,num_tx_queues = <0x8>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupt-parent = <&mpic>;

			phy-handle = <&phy1>;

			phy-handle = <&phy1>;

			phy-connection-type = "rgmii-id";

			phy-connection-type = "rgmii-id";

			queue-group@0 {

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0xb2000 0x1000>;

				interrupts = <31 2 32 2 33 2>;

			};

			queue-group@1 {

				#address-cells = <1>;

				#size-cells = <1>;

				reg = <0xb6000 0x1000>;

				interrupts = <25 2 26 2 27 2>;

			};

		};

		};

		usb@22000 {

		usb@22000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl-usb2-dr";

			reg = <0x22000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <28 0x2>;

			phy_type = "ulpi";

			phy_type = "ulpi";

		};

		};

		   it enables USB2. OTOH, U-Boot does create a new node

		   it enables USB2. OTOH, U-Boot does create a new node

		   when there isn't any. So, just comment it out.

		   when there isn't any. So, just comment it out.

		usb@23000 {

		usb@23000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl-usb2-dr";

			reg = <0x23000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <46 0x2>;

			phy_type = "ulpi";

			phy_type = "ulpi";

		};

		};

		*/

		*/

		sdhci@2e000 {

			compatible = "fsl,p1020-esdhc", "fsl,esdhc";

			reg = <0x2e000 0x1000>;

			interrupts = <72 0x2>;

			interrupt-parent = <&mpic>;

			/* Filled in by U-Boot */

			clock-frequency = <0>;

		};

		crypto@30000 {

			compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",

				     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";

			reg = <0x30000 0x10000>;

			interrupts = <45 2 58 2>;

			interrupt-parent = <&mpic>;

			fsl,num-channels = <4>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0xbfe>;

			fsl,descriptor-types-mask = <0x3ab0ebf>;

		};

		mpic: pic@40000 {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <0x40000 0x40000>;

			compatible = "chrp,open-pic";

			device_type = "open-pic";

		};

		msi@41600 {

			compatible = "fsl,p1020-msi", "fsl,mpic-msi";

			reg = <0x41600 0x80>;

			msi-available-ranges = <0 0x100>;

			interrupts = <

				0xe0 0

				0xe1 0

				0xe2 0

				0xe3 0

				0xe4 0

				0xe5 0

				0xe6 0

				0xe7 0>;

			interrupt-parent = <&mpic>;

		};

		global-utilities@e0000 {	//global utilities block

			compatible = "fsl,p1020-guts";

			reg = <0xe0000 0x1000>;

			fsl,has-rstcr;

		};

	};

	};

	pci0: pcie@ffe09000 {

	pci0: pcie@ffe09000 {

		compatible = "fsl,mpc8548-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0 0xffe09000 0 0x1000>;

		bus-range = <0 255>;

		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000

		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;

			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;

		clock-frequency = <33333333>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-parent = <&mpic>;

		interrupt-map = <

		interrupts = <16 2>;

			/* IDSEL 0x0 */

			0000 0x0 0x0 0x1 &mpic 0x4 0x1

			0000 0x0 0x0 0x2 &mpic 0x5 0x1

			0000 0x0 0x0 0x3 &mpic 0x6 0x1

			0000 0x0 0x0 0x4 &mpic 0x7 0x1

			>;

		pcie@0 {

		pcie@0 {

			reg = <0x0 0x0 0x0 0x0 0x0>;

			reg = <0x0 0x0 0x0 0x0 0x0>;

			#size-cells = <2>;

			#size-cells = <2>;

	};

	};

	pci1: pcie@ffe0a000 {

	pci1: pcie@ffe0a000 {

		compatible = "fsl,mpc8548-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0 0xffe0a000 0 0x1000>;

		bus-range = <0 255>;

		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000

		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;

			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;

		clock-frequency = <33333333>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-parent = <&mpic>;

		interrupt-map = <

		interrupts = <16 2>;

			/* IDSEL 0x0 */

			0000 0x0 0x0 0x1 &mpic 0x0 0x1

			0000 0x0 0x0 0x2 &mpic 0x1 0x1

			0000 0x0 0x0 0x3 &mpic 0x2 0x1

			0000 0x0 0x0 0x4 &mpic 0x3 0x1

			>;

		pcie@0 {

		pcie@0 {

			reg = <0x0 0x0 0x0 0x0 0x0>;

			reg = <0x0 0x0 0x0 0x0 0x0>;

			#size-cells = <2>;

			#size-cells = <2>;