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Commit 3cb27f38 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: remove an extra level of indirection in PCI ID list 



Add the PCI IDs directly in the pciidlist array instead of defining an
extra macro. The minor benefit from this is neater diffs when adding to
the end of the list.

v2: drop the "aka" comment (Ville)

Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446053589-21283-1-git-send-email-jani.nikula@intel.com
parent 608c1a52

drivers/gpu/drm/i915/i915_drv.c

+35 −38
Original line number Diff line number Diff line
@@ -400,44 +400,41 @@ static const struct intel_device_info intel_broxton_info = { 
 * and subvendor IDs, we need it to come before the more general IVB

 * PCI ID matches, otherwise we'll use the wrong info struct above.

 */

#define INTEL_PCI_IDS \

	INTEL_I830_IDS(&intel_i830_info),	\

	INTEL_I845G_IDS(&intel_845g_info),	\

	INTEL_I85X_IDS(&intel_i85x_info),	\

	INTEL_I865G_IDS(&intel_i865g_info),	\

	INTEL_I915G_IDS(&intel_i915g_info),	\

	INTEL_I915GM_IDS(&intel_i915gm_info),	\

	INTEL_I945G_IDS(&intel_i945g_info),	\

	INTEL_I945GM_IDS(&intel_i945gm_info),	\

	INTEL_I965G_IDS(&intel_i965g_info),	\

	INTEL_G33_IDS(&intel_g33_info),		\

	INTEL_I965GM_IDS(&intel_i965gm_info),	\

	INTEL_GM45_IDS(&intel_gm45_info), 	\

	INTEL_G45_IDS(&intel_g45_info), 	\

	INTEL_PINEVIEW_IDS(&intel_pineview_info),	\

	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),	\

	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),	\

	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),	\

	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),	\

	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \

	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),	\

	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),	\

	INTEL_HSW_D_IDS(&intel_haswell_d_info), \

	INTEL_HSW_M_IDS(&intel_haswell_m_info), \

	INTEL_VLV_M_IDS(&intel_valleyview_m_info),	\

	INTEL_VLV_D_IDS(&intel_valleyview_d_info),	\

	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),	\

	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),	\

	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),	\

	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \

	INTEL_CHV_IDS(&intel_cherryview_info),	\

	INTEL_SKL_GT1_IDS(&intel_skylake_info),	\

	INTEL_SKL_GT2_IDS(&intel_skylake_info),	\

	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),	\

	INTEL_BXT_IDS(&intel_broxton_info)



static const struct pci_device_id pciidlist[] = {		/* aka */

	INTEL_PCI_IDS,

static const struct pci_device_id pciidlist[] = {

	INTEL_I830_IDS(&intel_i830_info),

	INTEL_I845G_IDS(&intel_845g_info),

	INTEL_I85X_IDS(&intel_i85x_info),

	INTEL_I865G_IDS(&intel_i865g_info),

	INTEL_I915G_IDS(&intel_i915g_info),

	INTEL_I915GM_IDS(&intel_i915gm_info),

	INTEL_I945G_IDS(&intel_i945g_info),

	INTEL_I945GM_IDS(&intel_i945gm_info),

	INTEL_I965G_IDS(&intel_i965g_info),

	INTEL_G33_IDS(&intel_g33_info),

	INTEL_I965GM_IDS(&intel_i965gm_info),

	INTEL_GM45_IDS(&intel_gm45_info),

	INTEL_G45_IDS(&intel_g45_info),

	INTEL_PINEVIEW_IDS(&intel_pineview_info),

	INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),

	INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),

	INTEL_SNB_D_IDS(&intel_sandybridge_d_info),

	INTEL_SNB_M_IDS(&intel_sandybridge_m_info),

	INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */

	INTEL_IVB_M_IDS(&intel_ivybridge_m_info),

	INTEL_IVB_D_IDS(&intel_ivybridge_d_info),

	INTEL_HSW_D_IDS(&intel_haswell_d_info),

	INTEL_HSW_M_IDS(&intel_haswell_m_info),

	INTEL_VLV_M_IDS(&intel_valleyview_m_info),

	INTEL_VLV_D_IDS(&intel_valleyview_d_info),

	INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),

	INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),

	INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),

	INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),

	INTEL_CHV_IDS(&intel_cherryview_info),

	INTEL_SKL_GT1_IDS(&intel_skylake_info),

	INTEL_SKL_GT2_IDS(&intel_skylake_info),

	INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),

	INTEL_BXT_IDS(&intel_broxton_info),

	{0, 0, 0}

};