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Commit 3c3a7e61 authored Nov 23, 2016 by Rex Zhu Committed by Alex Deucher Dec 06, 2016

drm/amdgpu: fix bug mclk can't change on Polaris



the root cause is we gate the clock to uvd vcpu.
mclk's change should need the response from uvd if
it is power on.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 805b3ba8

drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -656,9 +656,11 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
		UVD_CGC_GATE__UDEC_DB_MASK \|
		UVD_CGC_GATE__UDEC_MP_MASK \|
		UVD_CGC_GATE__WCB_MASK \|
		UVD_CGC_GATE__VCPU_MASK \|
		UVD_CGC_GATE__JPEG_MASK \|
		UVD_CGC_GATE__SCPU_MASK);
		/* only in pg enabled, we can gate clock to vcpu*/
		if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
		data3 \|= UVD_CGC_GATE__VCPU_MASK;
		data3 &= ~UVD_CGC_GATE__REGS_MASK;
		data1 \|= suvd_flags;
		} else {

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+4 −1

Original line number	Diff line number	Diff line
		@@ -879,10 +879,13 @@ static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
		UVD_CGC_GATE__UDEC_DB_MASK \|
		UVD_CGC_GATE__UDEC_MP_MASK \|
		UVD_CGC_GATE__WCB_MASK \|
		UVD_CGC_GATE__VCPU_MASK \|
		UVD_CGC_GATE__JPEG_MASK \|
		UVD_CGC_GATE__SCPU_MASK \|
		UVD_CGC_GATE__JPEG2_MASK);
		/* only in pg enabled, we can gate clock to vcpu*/
		if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
		data3 \|= UVD_CGC_GATE__VCPU_MASK;

		data3 &= ~UVD_CGC_GATE__REGS_MASK;
		} else {
		data3 = 0;