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Commit 3c1dae0a authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: dpaux: Fix transfers larger than 4 bytes 



The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: 6b6b6042 ("drm/tegra: Add eDP support")
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent b787f68c

drivers/gpu/drm/tegra/dpaux.c

+8 −10
Original line number Diff line number Diff line
@@ -72,34 +72,32 @@ static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, 
static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,

				   size_t size)

{

	unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0);

	size_t i, j;



	for (i = 0; i < size; i += 4) {

		size_t num = min_t(size_t, size - i, 4);

	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {

		size_t num = min_t(size_t, size - i * 4, 4);

		unsigned long value = 0;



		for (j = 0; j < num; j++)

			value |= buffer[i + j] << (j * 8);

			value |= buffer[i * 4 + j] << (j * 8);



		tegra_dpaux_writel(dpaux, value, offset++);

		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));

	}

}



static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,

				  size_t size)

{

	unsigned long offset = DPAUX_DP_AUXDATA_READ(0);

	size_t i, j;



	for (i = 0; i < size; i += 4) {

		size_t num = min_t(size_t, size - i, 4);

	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {

		size_t num = min_t(size_t, size - i * 4, 4);

		unsigned long value;



		value = tegra_dpaux_readl(dpaux, offset++);

		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));



		for (j = 0; j < num; j++)

			buffer[i + j] = value >> (j * 8);

			buffer[i * 4 + j] = value >> (j * 8);

	}

}