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Commit 3c13e601 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi into next/dt 

ARM64: DT: Hisilicon SoC DT updates for 4.18v2

- Add mailbox, stub clock, CPU frequency scaling, thermal cooling
  management and pcie msi interruption support for hi3660
- Add LPC support for hip06 and hip07
- Add PCIe, usb and emmc support for hi3798cv200

* tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi

:
  arm64: dts: hi3798cv200: enable emmc support for poplar board
  arm64: dts: hi3798cv200: enable usb2 support for poplar board
  arm64: dts: hi3798cv200: enable PCIe support for poplar board
  arm64: dts: hisi: Enable Hisi LPC node for hip07
  arm64: dts: hisi: Enable Hisi LPC node for hip06
  arm64: dts: hi3660: Add pcie msi interrupt attribute
  arm64: dts: hi3660: Add thermal cooling management
  arm64: dts: hi3660: Add CPU frequency scaling support
  arm64: dts: hi3660: Add stub clock node
  arm64: dts: hi3660: Add mailbox node

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 823927bd bb61c536

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+147 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/hi3660-clock.h>

#include <dt-bindings/thermal/thermal.h>



/ {

	compatible = "hisilicon,hi3660";
@@ -62,6 +63,10 @@ 
			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

			capacity-dmips-mhz = <592>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;

			operating-points-v2 = <&cluster0_opp>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <110>;

		};



		cpu1: cpu@1 {
@@ -72,6 +77,8 @@ 
			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

			capacity-dmips-mhz = <592>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu2: cpu@2 {
@@ -82,6 +89,8 @@ 
			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

			capacity-dmips-mhz = <592>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu3: cpu@3 {
@@ -92,6 +101,8 @@ 
			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

			capacity-dmips-mhz = <592>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;

			operating-points-v2 = <&cluster0_opp>;

		};



		cpu4: cpu@100 {
@@ -102,6 +113,10 @@ 
			next-level-cache = <&A73_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;

			operating-points-v2 = <&cluster1_opp>;

			#cooling-cells = <2>;

			dynamic-power-coefficient = <550>;

		};



		cpu5: cpu@101 {
@@ -112,6 +127,8 @@ 
			next-level-cache = <&A73_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;

			operating-points-v2 = <&cluster1_opp>;

		};



		cpu6: cpu@102 {
@@ -122,6 +139,8 @@ 
			next-level-cache = <&A73_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;

			operating-points-v2 = <&cluster1_opp>;

		};



		cpu7: cpu@103 {
@@ -132,6 +151,8 @@ 
			next-level-cache = <&A73_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_1>;

			capacity-dmips-mhz = <1024>;

			clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;

			operating-points-v2 = <&cluster1_opp>;

		};



		idle-states {
@@ -174,6 +195,76 @@ 
		};

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp00 {

			opp-hz = /bits/ 64 <533000000>;

			opp-microvolt = <700000>;

			clock-latency-ns = <300000>;

		};



		opp01 {

			opp-hz = /bits/ 64 <999000000>;

			opp-microvolt = <800000>;

			clock-latency-ns = <300000>;

		};



		opp02 {

			opp-hz = /bits/ 64 <1402000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

		};



		opp03 {

			opp-hz = /bits/ 64 <1709000000>;

			opp-microvolt = <1000000>;

			clock-latency-ns = <300000>;

		};



		opp04 {

			opp-hz = /bits/ 64 <1844000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

	};



	cluster1_opp: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp10 {

			opp-hz = /bits/ 64 <903000000>;

			opp-microvolt = <700000>;

			clock-latency-ns = <300000>;

		};



		opp11 {

			opp-hz = /bits/ 64 <1421000000>;

			opp-microvolt = <800000>;

			clock-latency-ns = <300000>;

		};



		opp12 {

			opp-hz = /bits/ 64 <1805000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

		};



		opp13 {

			opp-hz = /bits/ 64 <2112000000>;

			opp-microvolt = <1000000>;

			clock-latency-ns = <300000>;

		};



		opp14 {

			opp-hz = /bits/ 64 <2362000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

	};



	gic: interrupt-controller@e82b0000 {

		compatible = "arm,gic-400";

		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
@@ -274,6 +365,21 @@ 
			#reset-cells = <2>;

		};



		mailbox: mailbox@e896b000 {

			compatible = "hisilicon,hi3660-mbox";

			reg = <0x0 0xe896b000 0x0 0x1000>;

			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;

			#mbox-cells = <3>;

		};



		stub_clock: stub_clock@e896b500 {

			compatible = "hisilicon,hi3660-stub-clk";

			reg = <0x0 0xe896b500 0x0 0x0100>;

			#clock-cells = <1>;

			mboxes = <&mailbox 13 3 0>;

		};



		dual_timer0: timer@fff14000 {

			compatible = "arm,sp804", "arm,primecell";

			reg = <0x0 0xfff14000 0x0 0x1000>;
@@ -872,6 +978,8 @@ 
				  0x0 0x02000000>;

			num-lanes = <1>;

			#interrupt-cells = <1>;

			interrupts = <0 283 4>;

			interrupt-names = "msi";

			interrupt-map-mask = <0xf800 0 0 7>;

			interrupt-map = <0x0 0 0 1

					 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
@@ -972,5 +1080,44 @@ 
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

			#thermal-sensor-cells = <1>;

		};



		thermal-zones {



			cls0: cls0 {

				polling-delay = <1000>;

				polling-delay-passive = <100>;

				sustainable-power = <4500>;



				/* sensor ID */

				thermal-sensors = <&tsensor 1>;



				trips {

					threshold: trip-point@0 {

						temperature = <65000>;

						hysteresis = <1000>;

						type = "passive";

					};



					target: trip-point@1 {

						temperature = <75000>;

						hysteresis = <1000>;

						type = "passive";

					};

				};



				cooling-maps {

					map0 {

						trip = <&target>;

						contribution = <1024>;

						cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

					};

					map1 {

						trip = <&target>;

						contribution = <512>;

						cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;

					};

				};

			};

		};

	};

};

arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts

+38 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 


#include <dt-bindings/gpio/gpio.h>

#include "hi3798cv200.dtsi"

#include "poplar-pinctrl.dtsi"



/ {

	model = "HiSilicon Poplar Development Board";
@@ -61,6 +62,33 @@ 
			default-state = "off";

		};

	};



	reg_pcie: regulator-pcie {

		compatible = "regulator-fixed";

		regulator-name = "3V3_PCIE0";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio6 7 0>;

		enable-active-high;

	};

};



&ehci {

	status = "okay";

};



&emmc {

	pinctrl-names = "default";

	pinctrl-0 = <&emmc_pins_1 &emmc_pins_2

		     &emmc_pins_3 &emmc_pins_4>;

	fifo-depth = <256>;

	clock-frequency = <200000000>;

	cap-mmc-highspeed;

	mmc-ddr-1_8v;

	mmc-hs200-1_8v;

	non-removable;

	bus-width = <8>;

	status = "okay";

};



&gmac1 {
@@ -146,6 +174,16 @@ 
	status = "okay";

};



&ohci {

	status = "okay";

};



&pcie {

	reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;

	vpcie-supply = <&reg_pcie>;

	status = "okay";

};



&sd0 {

	bus-width = <4>;

	cap-sd-highspeed;

arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi

+202 −3
Original line number Diff line number Diff line
@@ -8,7 +8,9 @@ 
 */



#include <dt-bindings/clock/histb-clock.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/reset/ti-syscon.h>



/ {
@@ -106,6 +108,113 @@ 
			#reset-cells = <2>;

		};



		perictrl: peripheral-controller@8a20000 {

			compatible = "hisilicon,hi3798cv200-perictrl", "syscon",

				     "simple-mfd";

			reg = <0x8a20000 0x1000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x8a20000 0x1000>;



			usb2_phy1: usb2-phy@120 {

				compatible = "hisilicon,hi3798cv200-usb2-phy";

				reg = <0x120 0x4>;

				clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;

				resets = <&crg 0xbc 4>;

				#address-cells = <1>;

				#size-cells = <0>;



				usb2_phy1_port0: phy@0 {

					reg = <0>;

					#phy-cells = <0>;

					resets = <&crg 0xbc 8>;

				};



				usb2_phy1_port1: phy@1 {

					reg = <1>;

					#phy-cells = <0>;

					resets = <&crg 0xbc 9>;

				};

			};



			usb2_phy2: usb2-phy@124 {

				compatible = "hisilicon,hi3798cv200-usb2-phy";

				reg = <0x124 0x4>;

				clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;

				resets = <&crg 0xbc 6>;

				#address-cells = <1>;

				#size-cells = <0>;



				usb2_phy2_port0: phy@0 {

					reg = <0>;

					#phy-cells = <0>;

					resets = <&crg 0xbc 10>;

				};

			};



			combphy0: phy@850 {

				compatible = "hisilicon,hi3798cv200-combphy";

				reg = <0x850 0x8>;

				#phy-cells = <1>;

				clocks = <&crg HISTB_COMBPHY0_CLK>;

				resets = <&crg 0x188 4>;

				assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;

				assigned-clock-rates = <100000000>;

				hisilicon,fixed-mode = <PHY_TYPE_USB3>;

			};



			combphy1: phy@858 {

				compatible = "hisilicon,hi3798cv200-combphy";

				reg = <0x858 0x8>;

				#phy-cells = <1>;

				clocks = <&crg HISTB_COMBPHY1_CLK>;

				resets = <&crg 0x188 12>;

				assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;

				assigned-clock-rates = <100000000>;

				hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;

			};

		};



		pmx0: pinconf@8a21000 {

			compatible = "pinconf-single";

			reg = <0x8a21000 0x180>;

			pinctrl-single,register-width = <32>;

			pinctrl-single,function-mask = <7>;

			pinctrl-single,gpio-range = <

				&range 0  8 2  /* GPIO 0 */

				&range 8  1 0  /* GPIO 1 */

				&range 9  4 2

				&range 13 1 0

				&range 14 1 1

				&range 15 1 0

				&range 16 5 0  /* GPIO 2 */

				&range 21 3 1

				&range 24 4 1  /* GPIO 3 */

				&range 28 2 2

				&range 86 1 1

				&range 87 1 0

				&range 30 4 2  /* GPIO 4 */

				&range 34 3 0

				&range 37 1 2

				&range 38 3 2  /* GPIO 6 */

				&range 41 5 0

				&range 46 8 1  /* GPIO 7 */

				&range 54 8 1  /* GPIO 8 */

				&range 64 7 1  /* GPIO 9 */

				&range 71 1 0

				&range 72 6 1  /* GPIO 10 */

				&range 78 1 0

				&range 79 1 1

				&range 80 6 1  /* GPIO 11 */

				&range 70 2 1

				&range 88 8 0  /* GPIO 12 */

			>;



			range: gpio-range {

				#pinctrl-single,gpio-range-cells = <3>;

			};

		};



		uart0: serial@8b00000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x8b00000 0x1000>;
@@ -205,12 +314,17 @@ 
		};



		emmc: mmc@9830000 {

			compatible = "snps,dw-mshc";

			compatible = "hisilicon,hi3798cv200-dw-mshc";

			reg = <0x9830000 0x10000>;

			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HISTB_MMC_CIU_CLK>,

				 <&crg HISTB_MMC_BIU_CLK>;

			clock-names = "ciu", "biu";

				 <&crg HISTB_MMC_BIU_CLK>,

				 <&crg HISTB_MMC_SAMPLE_CLK>,

				 <&crg HISTB_MMC_DRV_CLK>;

			clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";

			resets = <&crg 0xa0 4>;

			reset-names = "reset";

			status = "disabled";

		};



		gpio0: gpio@8b20000 {
@@ -221,6 +335,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 0 8>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -234,6 +349,13 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <

				&pmx0 0 8 1

				&pmx0 1 9 4

				&pmx0 5 13 1

				&pmx0 6 14 1

				&pmx0 7 15 1

			>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -247,6 +369,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -260,6 +383,12 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <

				&pmx0 0 24 4

				&pmx0 4 28 2

				&pmx0 6 86 1

				&pmx0 7 87 1

			>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -273,6 +402,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -299,6 +429,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -312,6 +443,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 46 8>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -325,6 +457,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 54 8>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -338,6 +471,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -351,6 +485,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -364,6 +499,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -377,6 +513,7 @@ 
			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

			gpio-ranges = <&pmx0 0 88 8>;

			clocks = <&crg HISTB_APB_CLK>;

			clock-names = "apb_pclk";

			status = "disabled";
@@ -419,5 +556,67 @@ 
			clocks = <&sysctrl HISTB_IR_CLK>;

			status = "disabled";

		};



		pcie: pcie@9860000 {

			compatible = "hisilicon,hi3798cv200-pcie";

			reg = <0x9860000 0x1000>,

			      <0x0 0x2000>,

			      <0x2000000 0x01000000>;

			reg-names = "control", "rc-dbi", "config";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			bus-range = <0 15>;

			num-lanes = <1>;

			ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000

				  0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;

			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HISTB_PCIE_AUX_CLK>,

				 <&crg HISTB_PCIE_PIPE_CLK>,

				 <&crg HISTB_PCIE_SYS_CLK>,

				 <&crg HISTB_PCIE_BUS_CLK>;

			clock-names = "aux", "pipe", "sys", "bus";

			resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;

			reset-names = "soft", "sys", "bus";

			phys = <&combphy1 PHY_TYPE_PCIE>;

			phy-names = "phy";

			status = "disabled";

		};



		ohci: ohci@9880000 {

			compatible = "generic-ohci";

			reg = <0x9880000 0x10000>;

			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HISTB_USB2_BUS_CLK>,

				 <&crg HISTB_USB2_12M_CLK>,

				 <&crg HISTB_USB2_48M_CLK>;

			clock-names = "bus", "clk12", "clk48";

			resets = <&crg 0xb8 12>;

			reset-names = "bus";

			phys = <&usb2_phy1_port0>;

			phy-names = "usb";

			status = "disabled";

		};



		ehci: ehci@9890000 {

			compatible = "generic-ehci";

			reg = <0x9890000 0x10000>;

			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg HISTB_USB2_BUS_CLK>,

				 <&crg HISTB_USB2_PHY_CLK>,

				 <&crg HISTB_USB2_UTMI_CLK>;

			clock-names = "bus", "phy", "utmi";

			resets = <&crg 0xb8 12>,

				 <&crg 0xb8 16>,

				 <&crg 0xb8 13>;

			reset-names = "bus", "phy", "utmi";

			phys = <&usb2_phy1_port0>;

			phy-names = "usb";

			status = "disabled";

		};

	};

};

arch/arm64/boot/dts/hisilicon/hip06-d03.dts

+8 −0
Original line number Diff line number Diff line
@@ -25,6 +25,14 @@ 
	chosen { };

};



&ipmi0 {

	status = "ok";

};



&uart0 {

	status = "ok";

};



&eth0 {

	status = "ok";

};

arch/arm64/boot/dts/hisilicon/hip06.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -350,6 +350,27 @@ 
		#size-cells = <2>;

		ranges;



		isa@a01b0000 {

			compatible = "hisilicon,hip06-lpc";

			#size-cells = <1>;

			#address-cells = <2>;

			reg = <0x0 0xa01b0000 0x0 0x1000>;



			ipmi0: bt@e4 {

				compatible = "ipmi-bt";

				device_type = "ipmi";

				reg = <0x01 0xe4 0x04>;

				status = "disabled";

			};



			uart0: lpc-uart@2f8 {

				compatible = "ns16550a";

				clock-frequency = <1843200>;

				reg = <0x01 0x2f8 0x08>;

				status = "disabled";

			};

		};



		refclk: refclk {

			compatible = "fixed-clock";

			clock-frequency = <50000000>;