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Commit 3bfd0c9c authored by Anton Blanchard's avatar Anton Blanchard Committed by Benjamin Herrenschmidt
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powerpc: Decode correct MSR bits in oops output 



On a 64bit book3s machine I have an oops from a system reset that
claims the book3e CE bit was set:

MSR: 8000000000021032 <ME,CE,IR,DR>  CR: 24004082  XER: 00000010

On a book3s machine system reset sets IBM bit 46 and 47 depending on
the power saving mode. Separate the definitions by type and for
completeness add the rest of the bits in.

Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent e1fc235d

arch/powerpc/kernel/process.c

+19 −3
Original line number Original line Diff line number Diff line
@@ -584,16 +584,32 @@ static struct regbit { 
	unsigned long bit;

	unsigned long bit;

	const char *name;

	const char *name;

} msr_bits[] = {

} msr_bits[] = {

#if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)

	{MSR_SF,	"SF"},

	{MSR_HV,	"HV"},

#endif

	{MSR_VEC,	"VEC"},

	{MSR_VSX,	"VSX"},

#ifdef CONFIG_BOOKE

	{MSR_CE,	"CE"},

#endif

	{MSR_EE,	"EE"},

	{MSR_EE,	"EE"},

	{MSR_PR,	"PR"},

	{MSR_PR,	"PR"},

	{MSR_FP,	"FP"},

	{MSR_FP,	"FP"},

	{MSR_VEC,	"VEC"},

	{MSR_VSX,	"VSX"},

	{MSR_ME,	"ME"},

	{MSR_ME,	"ME"},

	{MSR_CE,	"CE"},

#ifdef CONFIG_BOOKE

	{MSR_DE,	"DE"},

	{MSR_DE,	"DE"},

#else

	{MSR_SE,	"SE"},

	{MSR_BE,	"BE"},

#endif

	{MSR_IR,	"IR"},

	{MSR_IR,	"IR"},

	{MSR_DR,	"DR"},

	{MSR_DR,	"DR"},

	{MSR_PMM,	"PMM"},

#ifndef CONFIG_BOOKE

	{MSR_RI,	"RI"},

	{MSR_LE,	"LE"},

#endif

	{0,		NULL}

	{0,		NULL}

};

};