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Commit 3be192e9 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/skl: drop workarounds for E0 revision 



Pre-production hardware is not supported.

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/0633a02177195703502ef2396aab03efc0314334.1474034059.git.jani.nikula@intel.com
parent 9fc736e8

drivers/gpu/drm/i915/intel_lrc.c

+2 −3
Original line number Diff line number Diff line
@@ -845,13 +845,12 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, 
	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);



	/*

	 * WaDisableLSQCROPERFforOCL:skl,kbl

	 * WaDisableLSQCROPERFforOCL:kbl

	 * This WA is implemented in skl_init_clock_gating() but since

	 * this batch updates GEN8_L3SQCREG4 with default value we need to

	 * set this bit here to retain the WA during flush.

	 */

	if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) ||

	    IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))

	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))

		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;



	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |

drivers/gpu/drm/i915/intel_ringbuffer.c

+0 −14
Original line number Diff line number Diff line
@@ -1003,20 +1003,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) 
	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,

		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));



	if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {

		/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */

		I915_WRITE(FF_SLICE_CS_CHICKEN2,

			   _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));

	}



	/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes

	 * involving this register should also be added to WA batch as required.

	 */

	if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))

		/* WaDisableLSQCROPERFforOCL:skl */

		I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |

			   GEN8_LQSC_RO_PERF_DIS);



	/* WaEnableGapsTsvCreditFix:skl */

	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |

				   GEN9_GAPS_TSV_CREDIT_DISABLE));