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Commit 3b92e263 authored by Rodrigo Vivi's avatar Rodrigo Vivi
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drm/i915/cnp: Display Wa #1179: WaHardHangonHotPlug 



"CNL PCH chance of hang when software accesses south display
registers after hotplug is enabled.
Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
south display hotplug detection."

"Workaround only needs to be applied to pre-production steppings
used in graphics capable SKUs, but it is easier to apply to
everything, and does not hurt."

v2: Moving from clock gating to right before enabling
    SHOTPLUG_CTL as it should be.
v3: Align with SOUTH_CHICKEN1 (DK) and consequently use proper
    spaces on bits definition since other bits around already use
    new style. And now that checkpatch is not noise anymore I also
    fixed the reg read mask to avoid going over 80 chars.

Suggested-by: default avatarBen Widawsky <ben@bwidawsk.net>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170919215703.25947-1-rodrigo.vivi@intel.com
parent fb5f4e96

drivers/gpu/drm/i915/i915_irq.c

+9 −1
Original line number Diff line number Diff line
@@ -3218,7 +3218,15 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv) 


static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)

{

	u32 hotplug;

	u32 val, hotplug;



	/* Display WA #1179 WaHardHangonHotPlug: cnp */

	if (HAS_PCH_CNP(dev_priv)) {

		val = I915_READ(SOUTH_CHICKEN1);

		val &= ~CHASSIS_CLK_REQ_DURATION_MASK;

		val |= CHASSIS_CLK_REQ_DURATION(0xf);

		I915_WRITE(SOUTH_CHICKEN1, val);

	}



	/* Enable digital hotplug on the PCH */

	hotplug = I915_READ(PCH_PORT_HOTPLUG);

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -7471,6 +7471,8 @@ enum { 
#define  FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))

#define  FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))

#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)

#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)

#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)

#define  SPT_PWM_GRANULARITY		(1<<0)

#define SOUTH_CHICKEN2		_MMIO(0xc2004)

#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)