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Commit 3b2c0564 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'juno-scpi-for-v4.4' of... 

Merge tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt

Merge "SCPI support on ARM64 Juno Development Platform" from Sudeep Holla:

  1. SRAM, MHU mailbox and SCPI support
  2. CPU topology using cpu-map
  3. Clock support for all the cpus
  4. Support for SoC sensors

* tag 'juno-scpi-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: Add sensor node to Juno dt
  arm64: dts: add clock support for all the cpus
  arm64: dts: add CPU topology on Juno
  arm64: dts: add SRAM, MHU mailbox and SCPI support on Juno
parents 020effe8 dfacaf0e

arch/arm64/boot/dts/arm/juno-base.dtsi

+59 −0
Original line number Original line Diff line number Diff line
@@ -17,6 +17,18 @@ 
		};

		};

	};

	};





	mailbox: mhu@2b1f0000 {

		compatible = "arm,mhu", "arm,primecell";

		reg = <0x0 0x2b1f0000 0x0 0x1000>;

		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "mhu_lpri_rx",

				  "mhu_hpri_rx";

		#mbox-cells = <1>;

		clocks = <&soc_refclk100mhz>;

		clock-names = "apb_pclk";

	};



	gic: interrupt-controller@2c010000 {

	gic: interrupt-controller@2c010000 {

		compatible = "arm,gic-400", "arm,cortex-a15-gic";

		compatible = "arm,gic-400", "arm,cortex-a15-gic";

		reg = <0x0 0x2c010000 0 0x1000>,

		reg = <0x0 0x2c010000 0 0x1000>,
@@ -44,6 +56,53 @@ 
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;

	};

	};





	sram: sram@2e000000 {

		compatible = "arm,juno-sram-ns", "mmio-sram";

		reg = <0x0 0x2e000000 0x0 0x8000>;



		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x0 0x2e000000 0x8000>;



		cpu_scp_lpri: scp-shmem@0 {

			compatible = "arm,juno-scp-shmem";

			reg = <0x0 0x200>;

		};



		cpu_scp_hpri: scp-shmem@200 {

			compatible = "arm,juno-scp-shmem";

			reg = <0x200 0x200>;

		};

	};



	scpi {

		compatible = "arm,scpi";

		mboxes = <&mailbox 1>;

		shmem = <&cpu_scp_hpri>;



		clocks {

			compatible = "arm,scpi-clocks";



			scpi_dvfs: scpi_clocks@0 {

				compatible = "arm,scpi-dvfs-clocks";

				#clock-cells = <1>;

				clock-indices = <0>, <1>, <2>;

				clock-output-names = "atlclk", "aplclk","gpuclk";

			};

			scpi_clk: scpi_clocks@3 {

				compatible = "arm,scpi-variable-clocks";

				#clock-cells = <1>;

				clock-indices = <3>, <4>;

				clock-output-names = "pxlclk0", "pxlclk1";

			};

		};



		scpi_sensors0: sensors {

			compatible = "arm,scpi-sensors";

			#thermal-sensor-cells = <1>;

		};

	};



	/include/ "juno-clocks.dtsi"

	/include/ "juno-clocks.dtsi"





	dma@7ff00000 {

	dma@7ff00000 {

arch/arm64/boot/dts/arm/juno-r1.dts

+32 −0
Original line number Original line Diff line number Diff line
@@ -34,12 +34,39 @@ 
		#address-cells = <2>;

		#address-cells = <2>;

		#size-cells = <0>;

		#size-cells = <0>;





		cpu-map {

			cluster0 {

				core0 {

					cpu = <&A57_0>;

				};

				core1 {

					cpu = <&A57_1>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&A53_0>;

				};

				core1 {

					cpu = <&A53_1>;

				};

				core2 {

					cpu = <&A53_2>;

				};

				core3 {

					cpu = <&A53_3>;

				};

			};

		};



		A57_0: cpu@0 {

		A57_0: cpu@0 {

			compatible = "arm,cortex-a57","arm,armv8";

			compatible = "arm,cortex-a57","arm,armv8";

			reg = <0x0 0x0>;

			reg = <0x0 0x0>;

			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A57_L2>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

		};

		};





		A57_1: cpu@1 {

		A57_1: cpu@1 {
@@ -48,6 +75,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A57_L2>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

		};

		};





		A53_0: cpu@100 {

		A53_0: cpu@100 {
@@ -56,6 +84,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A53_1: cpu@101 {

		A53_1: cpu@101 {
@@ -64,6 +93,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A53_2: cpu@102 {

		A53_2: cpu@102 {
@@ -72,6 +102,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A53_3: cpu@103 {

		A53_3: cpu@103 {
@@ -80,6 +111,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A57_L2: l2-cache0 {

		A57_L2: l2-cache0 {

arch/arm64/boot/dts/arm/juno.dts

+32 −0
Original line number Original line Diff line number Diff line
@@ -34,12 +34,39 @@ 
		#address-cells = <2>;

		#address-cells = <2>;

		#size-cells = <0>;

		#size-cells = <0>;





		cpu-map {

			cluster0 {

				core0 {

					cpu = <&A57_0>;

				};

				core1 {

					cpu = <&A57_1>;

				};

			};



			cluster1 {

				core0 {

					cpu = <&A53_0>;

				};

				core1 {

					cpu = <&A53_1>;

				};

				core2 {

					cpu = <&A53_2>;

				};

				core3 {

					cpu = <&A53_3>;

				};

			};

		};



		A57_0: cpu@0 {

		A57_0: cpu@0 {

			compatible = "arm,cortex-a57","arm,armv8";

			compatible = "arm,cortex-a57","arm,armv8";

			reg = <0x0 0x0>;

			reg = <0x0 0x0>;

			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A57_L2>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

		};

		};





		A57_1: cpu@1 {

		A57_1: cpu@1 {
@@ -48,6 +75,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A57_L2>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

		};

		};





		A53_0: cpu@100 {

		A53_0: cpu@100 {
@@ -56,6 +84,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A53_1: cpu@101 {

		A53_1: cpu@101 {
@@ -64,6 +93,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A53_2: cpu@102 {

		A53_2: cpu@102 {
@@ -72,6 +102,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A53_3: cpu@103 {

		A53_3: cpu@103 {
@@ -80,6 +111,7 @@ 
			device_type = "cpu";

			device_type = "cpu";

			enable-method = "psci";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

		};

		};





		A57_L2: l2-cache0 {

		A57_L2: l2-cache0 {