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Commit 3b064e6f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'linux-4.18' of git://github.com/skeggsb/linux into drm-next 



The main thing here is the addition of support for Volta GV100 GPUs,
everything else basically restructuring display / graphics init code
to make it possible to fit Volta support in more nicely.

There's a bunch of improvements/fixes scattered in there for earlier
GPUs too, particularly graphics engine init on all GPUs from Fermi
onwards.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv7sjDKyR43n+6=iLC+ExGhBTLRLdKqwrhcfJWjEAndK0g@mail.gmail.com
parents 1fafef9d 6c46d01f

drivers/gpu/drm/nouveau/Kbuild

+3 −5
Original line number Diff line number Diff line
@@ -38,14 +38,16 @@ nouveau-y += nouveau_vmm.o 


# DRM - modesetting

nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o

nouveau-y += nouveau_bios.o

nouveau-y += nouveau_connector.o

nouveau-y += nouveau_display.o

nouveau-y += nv50_display.o

nouveau-y += nouveau_dp.o

nouveau-y += nouveau_fbcon.o

nouveau-y += nv04_fbcon.o

nouveau-y += nv50_fbcon.o

nouveau-y += nvc0_fbcon.o

include $(src)/dispnv04/Kbuild

include $(src)/dispnv50/Kbuild



# DRM - command submission

nouveau-y += nouveau_abi16.o
@@ -59,8 +61,4 @@ nouveau-y += nv50_fence.o 
nouveau-y += nv84_fence.o

nouveau-y += nvc0_fence.o



# DRM - prehistoric modesetting (NV04-G7x)

nouveau-y += nouveau_bios.o

include $(src)/dispnv04/Kbuild



obj-$(CONFIG_DRM_NOUVEAU) += nouveau.o

drivers/gpu/drm/nouveau/dispnv50/Kbuild

0 → 100644
+51 −0
Original line number Diff line number Diff line 
nouveau-y += dispnv50/disp.o

nouveau-y += dispnv50/lut.o



nouveau-y += dispnv50/core.o

nouveau-y += dispnv50/core507d.o

nouveau-y += dispnv50/core827d.o

nouveau-y += dispnv50/core907d.o

nouveau-y += dispnv50/core917d.o

nouveau-y += dispnv50/corec37d.o



nouveau-y += dispnv50/dac507d.o

nouveau-y += dispnv50/dac907d.o



nouveau-y += dispnv50/pior507d.o



nouveau-y += dispnv50/sor507d.o

nouveau-y += dispnv50/sor907d.o

nouveau-y += dispnv50/sorc37d.o



nouveau-y += dispnv50/head.o

nouveau-y += dispnv50/head507d.o

nouveau-y += dispnv50/head827d.o

nouveau-y += dispnv50/head907d.o

nouveau-y += dispnv50/head917d.o

nouveau-y += dispnv50/headc37d.o



nouveau-y += dispnv50/wimm.o

nouveau-y += dispnv50/wimmc37b.o



nouveau-y += dispnv50/wndw.o

nouveau-y += dispnv50/wndwc37e.o



nouveau-y += dispnv50/base.o

nouveau-y += dispnv50/base507c.o

nouveau-y += dispnv50/base827c.o

nouveau-y += dispnv50/base907c.o

nouveau-y += dispnv50/base917c.o



nouveau-y += dispnv50/curs.o

nouveau-y += dispnv50/curs507a.o

nouveau-y += dispnv50/curs907a.o

nouveau-y += dispnv50/cursc37a.o



nouveau-y += dispnv50/oimm.o

nouveau-y += dispnv50/oimm507b.o



nouveau-y += dispnv50/ovly.o

nouveau-y += dispnv50/ovly507e.o

nouveau-y += dispnv50/ovly827e.o

nouveau-y += dispnv50/ovly907e.o

nouveau-y += dispnv50/ovly917e.o

drivers/gpu/drm/nouveau/dispnv50/atom.h

0 → 100644
+222 −0
Original line number Diff line number Diff line 
#ifndef __NV50_KMS_ATOM_H__

#define __NV50_KMS_ATOM_H__

#define nv50_atom(p) container_of((p), struct nv50_atom, state)

#include <drm/drm_atomic.h>



struct nv50_atom {

	struct drm_atomic_state state;



	struct list_head outp;

	bool lock_core;

	bool flush_disable;

};



#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)



struct nv50_head_atom {

	struct drm_crtc_state state;



	struct {

		u32 mask;

		u32 olut;

	} wndw;



	struct {

		u16 iW;

		u16 iH;

		u16 oW;

		u16 oH;

	} view;



	struct nv50_head_mode {

		bool interlace;

		u32 clock;

		struct {

			u16 active;

			u16 synce;

			u16 blanke;

			u16 blanks;

		} h;

		struct {

			u32 active;

			u16 synce;

			u16 blanke;

			u16 blanks;

			u16 blank2s;

			u16 blank2e;

			u16 blankus;

		} v;

	} mode;



	struct {

		bool visible;

		u32 handle;

		u64 offset:40;

		u8 buffer:1;

		u8 mode:4;

		u8 size:2;

		u8 range:2;

		u8 output_mode:2;

	} olut;



	struct {

		bool visible;

		u32 handle;

		u64 offset:40;

		u8  format;

		u8  kind:7;

		u8  layout:1;

		u8  blockh:4;

		u16 blocks:12;

		u32 pitch:20;

		u16 x;

		u16 y;

		u16 w;

		u16 h;

	} core;



	struct {

		bool visible;

		u32 handle;

		u64 offset:40;

		u8  layout:2;

		u8  format:8;

	} curs;



	struct {

		u8  depth;

		u8  cpp;

		u16 x;

		u16 y;

		u16 w;

		u16 h;

	} base;



	struct {

		u8 cpp;

	} ovly;



	struct {

		bool enable:1;

		u8 bits:2;

		u8 mode:4;

	} dither;



	struct {

		struct {

			u16 cos:12;

			u16 sin:12;

		} sat;

	} procamp;



	struct {

		u8 nhsync:1;

		u8 nvsync:1;

		u8 depth:4;

	} or;



	union nv50_head_atom_mask {

		struct {

			bool olut:1;

			bool core:1;

			bool curs:1;

			bool view:1;

			bool mode:1;

			bool base:1;

			bool ovly:1;

			bool dither:1;

			bool procamp:1;

			bool or:1;

		};

		u16 mask;

	} set, clr;

};



static inline struct nv50_head_atom *

nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)

{

	struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);

	if (IS_ERR(statec))

		return (void *)statec;

	return nv50_head_atom(statec);

}



#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)



struct nv50_wndw_atom {

	struct drm_plane_state state;



	struct drm_property_blob *ilut;

	bool visible;



	struct {

		u32  handle;

		u16  offset:12;

		bool awaken:1;

	} ntfy;



	struct {

		u32 handle;

		u16 offset:12;

		u32 acquire;

		u32 release;

	} sema;



	struct {

		u32 handle;

		struct {

			u64 offset:40;

			u8  buffer:1;

			u8  enable:2;

			u8  mode:4;

			u8  size:2;

			u8  range:2;

			u8  output_mode:2;

		} i;

	} xlut;



	struct {

		u8  mode:2;

		u8  interval:4;



		u8  colorspace:2;

		u8  format;

		u8  kind:7;

		u8  layout:1;

		u8  blockh:4;

		u16 blocks[3];

		u32 pitch[3];

		u16 w;

		u16 h;



		u32 handle[6];

		u64 offset[6];

	} image;



	struct {

		u16 sx;

		u16 sy;

		u16 sw;

		u16 sh;

		u16 dw;

		u16 dh;

	} scale;



	struct {

		u16 x;

		u16 y;

	} point;



	union nv50_wndw_atom_mask {

		struct {

			bool ntfy:1;

			bool sema:1;

			bool xlut:1;

			bool image:1;

			bool scale:1;

			bool point:1;

		};

		u8 mask;

	} set, clr;

};

#endif

drivers/gpu/drm/nouveau/dispnv50/base.c

0 → 100644
+53 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 */

#include "base.h"



#include <nvif/class.h>



int

nv50_base_new(struct nouveau_drm *drm, int head, struct nv50_wndw **pwndw)

{

	struct {

		s32 oclass;

		int version;

		int (*new)(struct nouveau_drm *, int, s32, struct nv50_wndw **);

	} bases[] = {

		{ GK110_DISP_BASE_CHANNEL_DMA, 0, base917c_new },

		{ GK104_DISP_BASE_CHANNEL_DMA, 0, base917c_new },

		{ GF110_DISP_BASE_CHANNEL_DMA, 0, base907c_new },

		{ GT214_DISP_BASE_CHANNEL_DMA, 0, base827c_new },

		{ GT200_DISP_BASE_CHANNEL_DMA, 0, base827c_new },

		{   G82_DISP_BASE_CHANNEL_DMA, 0, base827c_new },

		{  NV50_DISP_BASE_CHANNEL_DMA, 0, base507c_new },

		{}

	};

	struct nv50_disp *disp = nv50_disp(drm->dev);

	int cid;



	cid = nvif_mclass(&disp->disp->object, bases);

	if (cid < 0) {

		NV_ERROR(drm, "No supported base class\n");

		return cid;

	}



	return bases[cid].new(drm, head, bases[cid].oclass, pwndw);

}

drivers/gpu/drm/nouveau/dispnv50/base.h

0 → 100644
+31 −0
Original line number Diff line number Diff line 
#ifndef __NV50_KMS_BASE_H__

#define __NV50_KMS_BASE_H__

#include "wndw.h"



int base507c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **);

int base507c_new_(const struct nv50_wndw_func *, const u32 *format,

		  struct nouveau_drm *, int head, s32 oclass,

		  u32 interlock_data, struct nv50_wndw **);

extern const u32 base507c_format[];

int base507c_acquire(struct nv50_wndw *, struct nv50_wndw_atom *,

		     struct nv50_head_atom *);

void base507c_release(struct nv50_wndw *, struct nv50_wndw_atom *,

		      struct nv50_head_atom *);

void base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *);

void base507c_sema_clr(struct nv50_wndw *);

void base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *);

void base507c_ntfy_clr(struct nv50_wndw *);

void base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *);

void base507c_xlut_clr(struct nv50_wndw *);

void base507c_image_clr(struct nv50_wndw *);

void base507c_update(struct nv50_wndw *, u32 *);



int base827c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **);



int base907c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **);

extern const struct nv50_wndw_func base907c;



int base917c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **);



int nv50_base_new(struct nouveau_drm *, int head, struct nv50_wndw **);

#endif