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Commit 3ae471f7 authored by Jean-Francois Moine's avatar Jean-Francois Moine Committed by Russell King
Browse files

drm/i2c: tda998x: set the PLL division factor in range 0..3 



The predivider division factor of the register PLL_SERIAL_2 is in the
range 0..3, the value 0 being used for a division by 1.

Tested-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Acked-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: default avatarJean-Francois Moine <moinejf@free.fr>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 2eb4c7b1

drivers/gpu/drm/i2c/tda998x_drv.c

+6 −1
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ struct tda998x_priv { 
# define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)

# define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)

#define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */

# define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0)

# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)

# define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)

#define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */

# define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
@@ -824,6 +824,11 @@ tda998x_encoder_mode_set(struct drm_encoder *encoder, 
	}



	div = 148500 / mode->clock;

	if (div != 0) {

		div--;

		if (div > 3)

			div = 3;

	}



	/* mute the audio FIFO: */

	reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);