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Commit 3aaf4d95 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld into drm-next 

Here are the Mali DP driver changes. They include the mali-dp specific
changes from Jose Abreu on crtc->mode_valid() as well as a couple of
patches for fixing the sharing of IRQ lines and use of DRM CMA helper
for framebuffer physical address calculation. Please pull!

* 'for-upstream/mali-dp' of git://linux-arm.org/linux-ld:
  drm/arm: mali-dp: Use CMA helper for plane buffer address calculation
  drm/mali-dp: Check PM status when sharing interrupt lines
  drm/arm: malidp: Use crtc->mode_valid() callback
parents d02b0ffb e40eda3d

drivers/gpu/drm/arm/malidp_crtc.c

+5 −6
Original line number Diff line number Diff line
@@ -22,9 +22,8 @@ 
#include "malidp_drv.h"

#include "malidp_hw.h"



static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc,

				   const struct drm_display_mode *mode,

				   struct drm_display_mode *adjusted_mode)

static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc,

						   const struct drm_display_mode *mode)

{

	struct malidp_drm *malidp = crtc_to_malidp_device(crtc);

	struct malidp_hw_device *hwdev = malidp->dev;
@@ -40,11 +39,11 @@ static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc, 
		if (rate != req_rate) {

			DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",

					 req_rate);

			return false;

			return MODE_NOCLOCK;

		}

	}



	return true;

	return MODE_OK;

}



static void malidp_crtc_enable(struct drm_crtc *crtc)
@@ -408,7 +407,7 @@ static int malidp_crtc_atomic_check(struct drm_crtc *crtc, 
}



static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {

	.mode_fixup = malidp_crtc_mode_fixup,

	.mode_valid = malidp_crtc_mode_valid,

	.enable = malidp_crtc_enable,

	.disable = malidp_crtc_disable,

	.atomic_check = malidp_crtc_atomic_check,

drivers/gpu/drm/arm/malidp_hw.c

+16 −3
Original line number Diff line number Diff line
@@ -766,12 +766,17 @@ static irqreturn_t malidp_de_irq(int irq, void *arg) 
	u32 status, mask, dc_status;

	irqreturn_t ret = IRQ_NONE;



	if (!drm->dev_private)

		return IRQ_HANDLED;



	hwdev = malidp->dev;

	de = &hwdev->map.de_irq_map;



	/*

	 * if we are suspended it is likely that we were invoked because

	 * we share an interrupt line with some other driver, don't try

	 * to read the hardware registers

	 */

	if (hwdev->pm_suspended)

		return IRQ_NONE;



	/* first handle the config valid IRQ */

	dc_status = malidp_hw_read(hwdev, hwdev->map.dc_base + MALIDP_REG_STATUS);

	if (dc_status & hwdev->map.dc_irq_map.vsync_irq) {
@@ -854,6 +859,14 @@ static irqreturn_t malidp_se_irq(int irq, void *arg) 
	struct malidp_hw_device *hwdev = malidp->dev;

	u32 status, mask;



	/*

	 * if we are suspended it is likely that we were invoked because

	 * we share an interrupt line with some other driver, don't try

	 * to read the hardware registers

	 */

	if (hwdev->pm_suspended)

		return IRQ_NONE;



	status = malidp_hw_read(hwdev, hwdev->map.se_base + MALIDP_REG_STATUS);

	if (!(status & hwdev->map.se_irq_map.irq_mask))

		return IRQ_NONE;

drivers/gpu/drm/arm/malidp_planes.c

+5 −7
Original line number Diff line number Diff line
@@ -264,11 +264,9 @@ static void malidp_de_set_plane_pitches(struct malidp_plane *mp, 
static void malidp_de_plane_update(struct drm_plane *plane,

				   struct drm_plane_state *old_state)

{

	struct drm_gem_cma_object *obj;

	struct malidp_plane *mp;

	const struct malidp_hw_regmap *map;

	struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);

	u16 ptr;

	u32 src_w, src_h, dest_w, dest_h, val;

	int i;
@@ -285,12 +283,12 @@ static void malidp_de_plane_update(struct drm_plane *plane, 


	for (i = 0; i < ms->n_planes; i++) {

		/* calculate the offset for the layer's plane registers */

		ptr = mp->layer->ptr + (i << 4);

		u16 ptr = mp->layer->ptr + (i << 4);

		dma_addr_t fb_addr = drm_fb_cma_get_gem_addr(plane->state->fb,

							     plane->state, i);



		obj = drm_fb_cma_get_gem_obj(plane->state->fb, i);

		obj->paddr += plane->state->fb->offsets[i];

		malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr);

		malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4);

		malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);

		malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);

	}

	malidp_de_set_plane_pitches(mp, ms->n_planes,

				    plane->state->fb->pitches);