Commit 3aa80ea4 authored Feb 05, 2014 by Will Deacon

iommu/arm-smmu: provide option to dsb macro when publishing tables



On coherent systems, publishing new page tables to the SMMU walker is
achieved with a dsb instruction. In fact, this can be a dsb(ishst) which
also provides the mandatory barrier option for arm64.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent b410aed9

drivers/iommu/arm-smmu.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -678,7 +678,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device smmu, void addr,

		/* Ensure new page tables are visible to the hardware walker */
		if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
		dsb();
		dsb(ishst);
		} else {
		/*
		* If the SMMU can't walk tables in the CPU caches, treat them