Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3a882143 authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark
Browse files

drm/msm/mdp5: Enable 3D mux in mdp5_ctl 



3D mux is a small block placed after the DSPPs in MDP5. It can merge
2 LM/DSPP outputs and feed it to a single interface.

Enable 3D Mux if our mdp5_pipeline has 2 active LMs. This check
will need to be made more specific later when we add Dual DSI
support with source split enabled. In that use case, each LM feeds to a
separae INTF, so the 3D mux isn't needed.

Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 0d1d3e44

drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c

+7 −2
Original line number Diff line number Diff line
@@ -138,9 +138,10 @@ static void set_display_intf(struct mdp5_kms *mdp5_kms, 
	spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);

}



static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_interface *intf)

static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline)

{

	unsigned long flags;

	struct mdp5_interface *intf = pipeline->intf;

	u32 ctl_op = 0;



	if (!mdp5_cfg_intf_is_virtual(intf->type))
@@ -161,6 +162,10 @@ static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_interface *intf) 
		break;

	}



	if (pipeline->r_mixer)

		ctl_op |= MDP5_CTL_OP_PACK_3D_ENABLE |

			  MDP5_CTL_OP_PACK_3D(1);



	spin_lock_irqsave(&ctl->hw_lock, flags);

	ctl_write(ctl, REG_MDP5_CTL_OP(ctl->id), ctl_op);

	spin_unlock_irqrestore(&ctl->hw_lock, flags);
@@ -183,7 +188,7 @@ int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) 
	if (!mdp5_cfg_intf_is_virtual(intf->type))

		set_display_intf(mdp5_kms, intf);



	set_ctl_op(ctl, intf);

	set_ctl_op(ctl, pipeline);



	return 0;

}