Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3a5df8ff authored by Andreas Herrmann's avatar Andreas Herrmann Committed by Will Deacon
Browse files

iommu/arm-smmu: support buggy implementations with secure cfg accesses 



In such a case we have to use secure aliases of some non-secure
registers.

This handling is switched on by DT property
"calxeda,smmu-secure-config-access" for an SMMU node.

Signed-off-by: default avatarAndreas Herrmann <andreas.herrmann@calxeda.com>
[will: merged with driver option handling patch]
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 636e97b0

drivers/iommu/arm-smmu.c

+48 −10
Original line number Diff line number Diff line
@@ -60,6 +60,16 @@ 
#define ARM_SMMU_GR0(smmu)		((smmu)->base)

#define ARM_SMMU_GR1(smmu)		((smmu)->base + (smmu)->pagesize)



/*

 * SMMU global address space with conditional offset to access secure

 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,

 * nsGFSYNR0: 0x450)

 */

#define ARM_SMMU_GR0_NS(smmu)						\

	((smmu)->base +							\

		((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)	\

			? 0x400 : 0))



/* Page table bits */

#define ARM_SMMU_PTE_XN			(((pteval_t)3) << 53)

#define ARM_SMMU_PTE_CONT		(((pteval_t)1) << 52)
@@ -351,6 +361,9 @@ struct arm_smmu_device { 
#define ARM_SMMU_FEAT_TRANS_S2		(1 << 3)

#define ARM_SMMU_FEAT_TRANS_NESTED	(1 << 4)

	u32				features;



#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)

	u32				options;

	int				version;



	u32				num_context_banks;
@@ -401,6 +414,29 @@ struct arm_smmu_domain { 
static DEFINE_SPINLOCK(arm_smmu_devices_lock);

static LIST_HEAD(arm_smmu_devices);



struct arm_smmu_option_prop {

	u32 opt;

	const char *prop;

};



static struct arm_smmu_option_prop arm_smmu_options [] = {

	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },

	{ 0, NULL},

};



static void parse_driver_options(struct arm_smmu_device *smmu)

{

	int i = 0;

	do {

		if (of_property_read_bool(smmu->dev->of_node,

						arm_smmu_options[i].prop)) {

			smmu->options |= arm_smmu_options[i].opt;

			dev_notice(smmu->dev, "option %s\n",

				arm_smmu_options[i].prop);

		}

	} while (arm_smmu_options[++i].opt);

}



static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,

						struct device_node *dev_node)

{
@@ -614,16 +650,16 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev) 
{

	u32 gfsr, gfsynr0, gfsynr1, gfsynr2;

	struct arm_smmu_device *smmu = dev;

	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);

	void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);



	gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);

	if (!gfsr)

		return IRQ_NONE;



	gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);

	gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);

	gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);



	if (!gfsr)

		return IRQ_NONE;



	dev_err_ratelimited(smmu->dev,

		"Unexpected global fault, this could be serious\n");

	dev_err_ratelimited(smmu->dev,
@@ -1597,9 +1633,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) 
	int i = 0;

	u32 reg;



	/* Clear Global FSR */

	reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);

	writel(reg, gr0_base + ARM_SMMU_GR0_sGFSR);

	/* clear global FSR */

	reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);

	writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);



	/* Mark all SMRn as invalid and all S2CRn as bypass */

	for (i = 0; i < smmu->num_mapping_groups; ++i) {
@@ -1619,7 +1655,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) 
	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);

	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);



	reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);

	reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);



	/* Enable fault reporting */

	reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
@@ -1638,7 +1674,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) 


	/* Push the button */

	arm_smmu_tlb_sync(smmu);

	writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sCR0);

	writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);

}



static int arm_smmu_id_size_to_bits(int size)
@@ -1885,6 +1921,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev) 
	if (err)

		goto out_put_parent;



	parse_driver_options(smmu);



	if (smmu->version > 1 &&

	    smmu->num_context_banks != smmu->num_context_irqs) {

		dev_err(dev,
@@ -1969,7 +2007,7 @@ static int arm_smmu_device_remove(struct platform_device *pdev) 
		free_irq(smmu->irqs[i], smmu);



	/* Turn the thing off */

	writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);

	writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);

	return 0;

}