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Commit 3a430067 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Michael Turquette
Browse files

clk: stm32mp1: add Debug clocks 



RCC manages clock for debug and trace.

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
parent 44cd455a

drivers/clk/clk-stm32mp1.c

+22 −0
Original line number Diff line number Diff line
@@ -260,6 +260,10 @@ static const char * const mco2_src[] = { 
	"ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"

};



static const char * const ck_trace_src[] = {

	"ck_axi"

};



static const struct clk_div_table axi_div_table[] = {

	{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },

	{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
@@ -280,6 +284,12 @@ static const struct clk_div_table apb_div_table[] = { 
	{ 0 },

};



static const struct clk_div_table ck_trace_div_table[] = {

	{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },

	{ 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },

	{ 0 },

};



#define MAX_MUX_CLK 2



struct stm32_mmux {
@@ -1980,6 +1990,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = { 
		  _GATE(RCC_MCO2CFGR, 12, 0),

		  _MUX(RCC_MCO2CFGR, 0, 3, 0),

		  _DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),



	/* Debug clocks */

	FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),



	GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),



	GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),



	COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,

		  _GATE(RCC_DBGCFGR, 9, 0),

		  _NO_MUX,

		  _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),

};



struct stm32_clock_match_data {