Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 39f3c23f authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Gregory CLEMENT
Browse files

ARM: dts: mvebu: armada-39x: update the SDHCI node on Armada 39x 



Commit 1140011e ("mmc: sdhci-pxav3: Modify clock settings
for the SDR50 and DDR50 modes") has extended the Device Tree
binding used to describe PXAv3 SDHCI controllers in order to be
able to use the SDR50 and DDR50 modes.

This commit updates the Device Tree description of the Armada
39x SDHCI controller in other to take advantage of this
functionality.

Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Acked-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 061492cf

arch/arm/boot/dts/armada-39x.dtsi

+4 −1
Original line number Original line Diff line number Diff line
@@ -356,7 +356,10 @@ 




			sdhci@d8000 {

			sdhci@d8000 {

				compatible = "marvell,armada-380-sdhci";

				compatible = "marvell,armada-380-sdhci";

				reg = <0xd8000 0x1000>, <0xdc000 0x100>;

				reg-names = "sdhci", "mbus", "conf-sdio3";

				reg = <0xd8000 0x1000>,

					<0xdc000 0x100>,

					<0x18454 0x4>;

				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gateclk 17>;

				clocks = <&gateclk 17>;

				mrvl,clk-delay-cycles = <0x1F>;

				mrvl,clk-delay-cycles = <0x1F>;