Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 39bc66c9 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
Browse files

drm/i915: Fix the SCC/SSC typo in the SPLL bits definition 



We're talking about Spread Spectrum Clocks here, thus SSC.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1ce42920

drivers/gpu/drm/i915/i915_reg.h

+3 −3
Original line number Original line Diff line number Diff line
@@ -4496,8 +4496,8 @@ 
/* SPLL */

/* SPLL */

#define SPLL_CTL			0x46020

#define SPLL_CTL			0x46020

#define  SPLL_PLL_ENABLE		(1<<31)

#define  SPLL_PLL_ENABLE		(1<<31)

#define  SPLL_PLL_SCC			(1<<28)

#define  SPLL_PLL_SSC			(1<<28)

#define  SPLL_PLL_NON_SCC		(2<<28)

#define  SPLL_PLL_NON_SSC		(2<<28)

#define  SPLL_PLL_FREQ_810MHz		(0<<26)

#define  SPLL_PLL_FREQ_810MHz		(0<<26)

#define  SPLL_PLL_FREQ_1350MHz		(1<<26)

#define  SPLL_PLL_FREQ_1350MHz		(1<<26)
@@ -4506,7 +4506,7 @@ 
#define WRPLL_CTL2			0x46060

#define WRPLL_CTL2			0x46060

#define  WRPLL_PLL_ENABLE		(1<<31)

#define  WRPLL_PLL_ENABLE		(1<<31)

#define  WRPLL_PLL_SELECT_SSC		(0x01<<28)

#define  WRPLL_PLL_SELECT_SSC		(0x01<<28)

#define  WRPLL_PLL_SELECT_NON_SCC	(0x02<<28)

#define  WRPLL_PLL_SELECT_NON_SSC	(0x02<<28)

#define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)

#define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)

/* WRPLL divider programming */

/* WRPLL divider programming */

#define  WRPLL_DIVIDER_REFERENCE(x)	((x)<<0)

#define  WRPLL_DIVIDER_REFERENCE(x)	((x)<<0)

drivers/gpu/drm/i915/intel_ddi.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -814,7 +814,7 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock) 
		WARN(I915_READ(reg) & SPLL_PLL_ENABLE,

		WARN(I915_READ(reg) & SPLL_PLL_ENABLE,

		     "SPLL already enabled\n");

		     "SPLL already enabled\n");





		val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SCC;

		val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;





	} else {

	} else {

		WARN(1, "Invalid DDI encoder type %d\n", type);

		WARN(1, "Invalid DDI encoder type %d\n", type);