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Commit 39ba1bb4 authored by Antoine Tenart's avatar Antoine Tenart Committed by Herbert Xu
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crypto: inside-secure - fix incorrect DSE data cache setting 



Set the correct value to the DSE data cache, using WR_CACHE_3BITS
instead of RD_CACHE_3BITS. This fixes an incorrect setting and helps
improving performances.

Reported-by: default avatarIgal Liberman <igall@marvell.com>
Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent aefa794e

drivers/crypto/inside-secure/safexcel.c

+1 −1
Original line number Diff line number Diff line
@@ -328,7 +328,7 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv) 
	/* DMA transfer size to use */

	val = EIP197_HIA_DSE_CFG_DIS_DEBUG;

	val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) | EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8);

	val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS);

	val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);

	writel(val, priv->base + EIP197_HIA_DSE_CFG);



	/* Leave the DSE threads reset state */