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Commit 393eb79a authored by Madhavan Srinivasan's avatar Madhavan Srinivasan Committed by Michael Ellerman
Browse files

powerpc/perf: factor out power8 __init_pmu code 



Factor out the power8 pmu init functions to share with
power9. Monitor Mode Control Register S(MMCRS) and
Monitor Mode Control Register H(MMCRH) registers are
dropped in Power9. These registers are added to new
function which are included for power8 init.

Signed-off-by: default avatarMadhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 7ffd948f

arch/powerpc/kernel/cpu_setup_power.S

+17 −1
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ _GLOBAL(__setup_cpu_power8) 
	mflr	r11

	bl	__init_FSCR

	bl	__init_PMU

	bl	__init_PMU_ISA207

	bl	__init_hvmode_206

	mtlr	r11

	beqlr
@@ -62,6 +63,7 @@ _GLOBAL(__setup_cpu_power8) 
	bl	__init_HFSCR

	bl	__init_tlb_power8

	bl	__init_PMU_HV

	bl	__init_PMU_HV_ISA207

	mtlr	r11

	blr
@@ -69,6 +71,7 @@ _GLOBAL(__restore_cpu_power8) 
	mflr	r11

	bl	__init_FSCR

	bl	__init_PMU

	bl	__init_PMU_ISA207

	mfmsr	r3

	rldicl.	r0,r3,4,63

	mtlr	r11
@@ -81,12 +84,14 @@ _GLOBAL(__restore_cpu_power8) 
	bl	__init_HFSCR

	bl	__init_tlb_power8

	bl	__init_PMU_HV

	bl	__init_PMU_HV_ISA207

	mtlr	r11

	blr



_GLOBAL(__setup_cpu_power9)

	mflr	r11

	bl	__init_FSCR

	bl	__init_PMU

	bl	__init_hvmode_206

	mtlr	r11

	beqlr
@@ -97,12 +102,14 @@ _GLOBAL(__setup_cpu_power9) 
	bl	__init_LPCR

	bl	__init_HFSCR

	bl	__init_tlb_power9

	bl	__init_PMU_HV

	mtlr	r11

	blr



_GLOBAL(__restore_cpu_power9)

	mflr	r11

	bl	__init_FSCR

	bl	__init_PMU

	mfmsr	r3

	rldicl.	r0,r3,4,63

	mtlr	r11
@@ -114,6 +121,7 @@ _GLOBAL(__restore_cpu_power9) 
	bl	__init_LPCR

	bl	__init_HFSCR

	bl	__init_tlb_power9

	bl	__init_PMU_HV

	mtlr	r11

	blr
@@ -208,14 +216,22 @@ __init_tlb_power9: 
__init_PMU_HV:

	li	r5,0

	mtspr	SPRN_MMCRC,r5

	blr



__init_PMU_HV_ISA207:

	li	r5,0

	mtspr	SPRN_MMCRH,r5

	blr



__init_PMU:

	li	r5,0

	mtspr	SPRN_MMCRS,r5

	mtspr	SPRN_MMCRA,r5

	mtspr	SPRN_MMCR0,r5

	mtspr	SPRN_MMCR1,r5

	mtspr	SPRN_MMCR2,r5

	blr



__init_PMU_ISA207:

	li	r5,0

	mtspr	SPRN_MMCRS,r5

	blr