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Commit 38dc0703 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Tomi Valkeinen
Browse files

drm: omapdrm: Move reg_fields to dispc_features structure 



The reg_fields feature describes DISPC registers only. Move it from the
omap_dss_features structure to the dispc_features structure.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 6d85d4ad

drivers/gpu/drm/omapdrm/dss/dispc.c

+76 −11
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ struct dispc_features { 
		u16 width, u16 height, u16 out_width, u16 out_height,

		bool mem_to_mem);

	u8 num_fifos;

	const struct dss_reg_field *reg_fields;

	const unsigned int num_reg_fields;

	const enum omap_overlay_caps *overlay_caps;

	const u32 **supported_color_modes;

	unsigned int num_mgrs;
@@ -188,6 +190,17 @@ enum mgr_reg_fields { 
	DISPC_MGR_FLD_NUM,

};



/* DISPC register field id */

enum dispc_feat_reg_field {

	FEAT_REG_FIRHINC,

	FEAT_REG_FIRVINC,

	FEAT_REG_FIFOHIGHTHRESHOLD,

	FEAT_REG_FIFOLOWTHRESHOLD,

	FEAT_REG_FIFOSIZE,

	FEAT_REG_HORIZONTALACCU,

	FEAT_REG_VERTICALACCU,

};



struct dispc_reg_field {

	u16 reg;

	u8 high;
@@ -361,6 +374,16 @@ static int dispc_get_num_mgrs(void) 
	return dispc.feat->num_mgrs;

}



static void dispc_get_reg_field(enum dispc_feat_reg_field id,

				u8 *start, u8 *end)

{

	if (id >= dispc.feat->num_reg_fields)

		BUG();



	*start = dispc.feat->reg_fields[id].start;

	*end = dispc.feat->reg_fields[id].end;

}



#define SR(reg) \

	dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)

#define RR(reg) \
@@ -1252,7 +1275,7 @@ static void dispc_init_fifos(void) 


	unit = dispc.feat->buffer_size_unit;



	dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);

	dispc_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);



	for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {

		size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
@@ -1342,8 +1365,8 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 
	low /= unit;

	high /= unit;



	dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);

	dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);

	dispc_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);

	dispc_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);



	DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",

			plane,
@@ -1510,10 +1533,8 @@ static void dispc_ovl_set_fir(enum omap_plane_id plane, 
	if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {

		u8 hinc_start, hinc_end, vinc_start, vinc_end;



		dss_feat_get_reg_field(FEAT_REG_FIRHINC,

					&hinc_start, &hinc_end);

		dss_feat_get_reg_field(FEAT_REG_FIRVINC,

					&vinc_start, &vinc_end);

		dispc_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);

		dispc_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);

		val = FLD_VAL(vinc, vinc_start, vinc_end) |

				FLD_VAL(hinc, hinc_start, hinc_end);
@@ -1530,8 +1551,8 @@ static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu, 
	u32 val;

	u8 hor_start, hor_end, vert_start, vert_end;



	dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);

	dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);

	dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);

	dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);



	val = FLD_VAL(vaccu, vert_start, vert_end) |

			FLD_VAL(haccu, hor_start, hor_end);
@@ -1545,8 +1566,8 @@ static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu, 
	u32 val;

	u8 hor_start, hor_end, vert_start, vert_end;



	dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);

	dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);

	dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);

	dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);



	val = FLD_VAL(vaccu, vert_start, vert_end) |

			FLD_VAL(haccu, hor_start, hor_end);
@@ -3711,6 +3732,36 @@ static void _omap_dispc_initial_config(void) 
		dispc_init_mflag();

}



static const struct dss_reg_field omap2_dispc_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 11, 0 },

	[FEAT_REG_FIRVINC]			= { 27, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]		= { 8, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 24, 16 },

	[FEAT_REG_FIFOSIZE]			= { 8, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 9, 0 },

	[FEAT_REG_VERTICALACCU]			= { 25, 16 },

};



static const struct dss_reg_field omap3_dispc_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 12, 0 },

	[FEAT_REG_FIRVINC]			= { 28, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]		= { 11, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 27, 16 },

	[FEAT_REG_FIFOSIZE]			= { 10, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 9, 0 },

	[FEAT_REG_VERTICALACCU]			= { 25, 16 },

};



static const struct dss_reg_field omap4_dispc_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 12, 0 },

	[FEAT_REG_FIRVINC]			= { 28, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]		= { 15, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 31, 16 },

	[FEAT_REG_FIFOSIZE]			= { 15, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 10, 0 },

	[FEAT_REG_VERTICALACCU]			= { 26, 16 },

};



static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = {

	/* OMAP_DSS_GFX */

	OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION,
@@ -3890,6 +3941,8 @@ static const struct dispc_features omap24xx_dispc_feats = { 
	.calc_scaling		=	dispc_ovl_calc_scaling_24xx,

	.calc_core_clk		=	calc_core_clk_24xx,

	.num_fifos		=	3,

	.reg_fields		=	omap2_dispc_reg_fields,

	.num_reg_fields		=	ARRAY_SIZE(omap2_dispc_reg_fields),

	.overlay_caps		=	omap2_dispc_overlay_caps,

	.supported_color_modes	=	omap2_dispc_supported_color_modes,

	.num_mgrs		=	2,
@@ -3917,6 +3970,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { 
	.calc_scaling		=	dispc_ovl_calc_scaling_34xx,

	.calc_core_clk		=	calc_core_clk_34xx,

	.num_fifos		=	3,

	.reg_fields		=	omap3_dispc_reg_fields,

	.num_reg_fields		=	ARRAY_SIZE(omap3_dispc_reg_fields),

	.overlay_caps		=	omap3430_dispc_overlay_caps,

	.supported_color_modes	=	omap3_dispc_supported_color_modes,

	.num_mgrs		=	2,
@@ -3944,6 +3999,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { 
	.calc_scaling		=	dispc_ovl_calc_scaling_34xx,

	.calc_core_clk		=	calc_core_clk_34xx,

	.num_fifos		=	3,

	.reg_fields		=	omap3_dispc_reg_fields,

	.num_reg_fields		=	ARRAY_SIZE(omap3_dispc_reg_fields),

	.overlay_caps		=	omap3430_dispc_overlay_caps,

	.supported_color_modes	=	omap3_dispc_supported_color_modes,

	.num_mgrs		=	2,
@@ -3971,6 +4028,8 @@ static const struct dispc_features omap36xx_dispc_feats = { 
	.calc_scaling		=	dispc_ovl_calc_scaling_34xx,

	.calc_core_clk		=	calc_core_clk_34xx,

	.num_fifos		=	3,

	.reg_fields		=	omap3_dispc_reg_fields,

	.num_reg_fields		=	ARRAY_SIZE(omap3_dispc_reg_fields),

	.overlay_caps		=	omap3630_dispc_overlay_caps,

	.supported_color_modes	=	omap3_dispc_supported_color_modes,

	.num_mgrs		=	2,
@@ -3998,6 +4057,8 @@ static const struct dispc_features am43xx_dispc_feats = { 
	.calc_scaling		=	dispc_ovl_calc_scaling_34xx,

	.calc_core_clk		=	calc_core_clk_34xx,

	.num_fifos		=	3,

	.reg_fields		=	omap3_dispc_reg_fields,

	.num_reg_fields		=	ARRAY_SIZE(omap3_dispc_reg_fields),

	.overlay_caps		=	omap3430_dispc_overlay_caps,

	.supported_color_modes	=	omap3_dispc_supported_color_modes,

	.num_mgrs		=	1,
@@ -4025,6 +4086,8 @@ static const struct dispc_features omap44xx_dispc_feats = { 
	.calc_scaling		=	dispc_ovl_calc_scaling_44xx,

	.calc_core_clk		=	calc_core_clk_44xx,

	.num_fifos		=	5,

	.reg_fields		=	omap4_dispc_reg_fields,

	.num_reg_fields		=	ARRAY_SIZE(omap4_dispc_reg_fields),

	.overlay_caps		=	omap4_dispc_overlay_caps,

	.supported_color_modes	=	omap4_dispc_supported_color_modes,

	.num_mgrs		=	3,
@@ -4057,6 +4120,8 @@ static const struct dispc_features omap54xx_dispc_feats = { 
	.calc_scaling		=	dispc_ovl_calc_scaling_44xx,

	.calc_core_clk		=	calc_core_clk_44xx,

	.num_fifos		=	5,

	.reg_fields		=	omap4_dispc_reg_fields,

	.num_reg_fields		=	ARRAY_SIZE(omap4_dispc_reg_fields),

	.overlay_caps		=	omap4_dispc_overlay_caps,

	.supported_color_modes	=	omap4_dispc_supported_color_modes,

	.num_mgrs		=	4,

drivers/gpu/drm/omapdrm/dss/dss_features.c

+0 −89
Original line number Diff line number Diff line
@@ -33,9 +33,6 @@ struct dss_param_range { 
};



struct omap_dss_features {

	const struct dss_reg_field *reg_fields;

	const int num_reg_fields;



	const enum dss_feat_id *features;

	const int num_features;
@@ -46,56 +43,6 @@ struct omap_dss_features { 
/* This struct is assigned to one of the below during initialization */

static const struct omap_dss_features *omap_current_dss_features;



static const struct dss_reg_field omap2_dss_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 11, 0 },

	[FEAT_REG_FIRVINC]			= { 27, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]		= { 8, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 24, 16 },

	[FEAT_REG_FIFOSIZE]			= { 8, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 9, 0 },

	[FEAT_REG_VERTICALACCU]			= { 25, 16 },

};



static const struct dss_reg_field omap3_dss_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 12, 0 },

	[FEAT_REG_FIRVINC]			= { 28, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]		= { 11, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 27, 16 },

	[FEAT_REG_FIFOSIZE]			= { 10, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 9, 0 },

	[FEAT_REG_VERTICALACCU]			= { 25, 16 },

};



static const struct dss_reg_field am43xx_dss_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 12, 0 },

	[FEAT_REG_FIRVINC]			= { 28, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]	= { 11, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 27, 16 },

	[FEAT_REG_FIFOSIZE]		= { 10, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 9, 0 },

	[FEAT_REG_VERTICALACCU]			= { 25, 16 },

};



static const struct dss_reg_field omap4_dss_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 12, 0 },

	[FEAT_REG_FIRVINC]			= { 28, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]		= { 15, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 31, 16 },

	[FEAT_REG_FIFOSIZE]			= { 15, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 10, 0 },

	[FEAT_REG_VERTICALACCU]			= { 26, 16 },

};



static const struct dss_reg_field omap5_dss_reg_fields[] = {

	[FEAT_REG_FIRHINC]			= { 12, 0 },

	[FEAT_REG_FIRVINC]			= { 28, 16 },

	[FEAT_REG_FIFOLOWTHRESHOLD]		= { 15, 0 },

	[FEAT_REG_FIFOHIGHTHRESHOLD]		= { 31, 16 },

	[FEAT_REG_FIFOSIZE]			= { 15, 0 },

	[FEAT_REG_HORIZONTALACCU]		= { 10, 0 },

	[FEAT_REG_VERTICALACCU]			= { 26, 16 },

};



static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {

	/* OMAP_DSS_CHANNEL_LCD */

	OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
@@ -358,9 +305,6 @@ static const enum dss_feat_id omap5_dss_feat_list[] = { 


/* OMAP2 DSS Features */

static const struct omap_dss_features omap2_dss_features = {

	.reg_fields = omap2_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),



	.features = omap2_dss_feat_list,

	.num_features = ARRAY_SIZE(omap2_dss_feat_list),
@@ -370,9 +314,6 @@ static const struct omap_dss_features omap2_dss_features = { 


/* OMAP3 DSS Features */

static const struct omap_dss_features omap3430_dss_features = {

	.reg_fields = omap3_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),



	.features = omap3430_dss_feat_list,

	.num_features = ARRAY_SIZE(omap3430_dss_feat_list),
@@ -385,9 +326,6 @@ static const struct omap_dss_features omap3430_dss_features = { 
 * vdds_dsi regulator.

 */

static const struct omap_dss_features am35xx_dss_features = {

	.reg_fields = omap3_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),



	.features = am35xx_dss_feat_list,

	.num_features = ARRAY_SIZE(am35xx_dss_feat_list),
@@ -396,9 +334,6 @@ static const struct omap_dss_features am35xx_dss_features = { 
};



static const struct omap_dss_features am43xx_dss_features = {

	.reg_fields = am43xx_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields),



	.features = am43xx_dss_feat_list,

	.num_features = ARRAY_SIZE(am43xx_dss_feat_list),
@@ -407,9 +342,6 @@ static const struct omap_dss_features am43xx_dss_features = { 
};



static const struct omap_dss_features omap3630_dss_features = {

	.reg_fields = omap3_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),



	.features = omap3630_dss_feat_list,

	.num_features = ARRAY_SIZE(omap3630_dss_feat_list),
@@ -420,9 +352,6 @@ static const struct omap_dss_features omap3630_dss_features = { 
/* OMAP4 DSS Features */

/* For OMAP4430 ES 1.0 revision */

static const struct omap_dss_features omap4430_es1_0_dss_features  = {

	.reg_fields = omap4_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),



	.features = omap4430_es1_0_dss_feat_list,

	.num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
@@ -432,9 +361,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = { 


/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */

static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {

	.reg_fields = omap4_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),



	.features = omap4430_es2_0_1_2_dss_feat_list,

	.num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
@@ -444,9 +370,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { 


/* For all the other OMAP4 versions */

static const struct omap_dss_features omap4_dss_features = {

	.reg_fields = omap4_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),



	.features = omap4_dss_feat_list,

	.num_features = ARRAY_SIZE(omap4_dss_feat_list),
@@ -456,9 +379,6 @@ static const struct omap_dss_features omap4_dss_features = { 


/* OMAP5 DSS Features */

static const struct omap_dss_features omap5_dss_features = {

	.reg_fields = omap5_dss_reg_fields,

	.num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),



	.features = omap5_dss_feat_list,

	.num_features = ARRAY_SIZE(omap5_dss_feat_list),
@@ -497,15 +417,6 @@ bool dss_has_feature(enum dss_feat_id id) 
	return false;

}



void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)

{

	if (id >= omap_current_dss_features->num_reg_fields)

		BUG();



	*start = omap_current_dss_features->reg_fields[id].start;

	*end = omap_current_dss_features->reg_fields[id].end;

}



void dss_features_init(enum omapdss_version version)

{

	switch (version) {

drivers/gpu/drm/omapdrm/dss/dss_features.h

+0 −12
Original line number Diff line number Diff line
@@ -64,17 +64,6 @@ enum dss_feat_id { 
	FEAT_MFLAG,

};



/* DSS register field id */

enum dss_feat_reg_field {

	FEAT_REG_FIRHINC,

	FEAT_REG_FIRVINC,

	FEAT_REG_FIFOHIGHTHRESHOLD,

	FEAT_REG_FIFOLOWTHRESHOLD,

	FEAT_REG_FIFOSIZE,

	FEAT_REG_HORIZONTALACCU,

	FEAT_REG_VERTICALACCU,

};



enum dss_range_param {

	FEAT_PARAM_DSS_FCK,

	FEAT_PARAM_DSS_PCD,
@@ -89,7 +78,6 @@ unsigned long dss_feat_get_param_min(enum dss_range_param param); 
unsigned long dss_feat_get_param_max(enum dss_range_param param);



bool dss_has_feature(enum dss_feat_id id);

void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);

void dss_features_init(enum omapdss_version version);



enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);