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Commit 387720c9 authored by Marc Zyngier's avatar Marc Zyngier Committed by Arnd Bergmann
Browse files

ARM: DTS: Fix register map for virt-capable GIC 



Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.

Acked-by: default avatarShawn Guo <shawnguo@kernel.org>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Acked-by: default avatarSantosh Shilimkar <ssantosh@kernel.org>
Acked-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 1defa60e

arch/arm/boot/dts/alpine.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ 
			interrupt-controller;

			reg = <0x0 0xfb001000 0x0 0x1000>,

			      <0x0 0xfb002000 0x0 0x2000>,

			      <0x0 0xfb004000 0x0 0x1000>,

			      <0x0 0xfb004000 0x0 0x2000>,

			      <0x0 0xfb006000 0x0 0x2000>;

			interrupts =

				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

arch/arm/boot/dts/axm55xx.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ 
		#address-cells = <0>;

		interrupt-controller;

		reg = <0x20 0x01001000 0 0x1000>,

		      <0x20 0x01002000 0 0x1000>,

		      <0x20 0x01002000 0 0x2000>,

		      <0x20 0x01004000 0 0x2000>,

		      <0x20 0x01006000 0 0x2000>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |

arch/arm/boot/dts/dra7.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ 
		interrupt-controller;

		#interrupt-cells = <3>;

		reg = <0x0 0x48211000 0x0 0x1000>,

		      <0x0 0x48212000 0x0 0x1000>,

		      <0x0 0x48212000 0x0 0x2000>,

		      <0x0 0x48214000 0x0 0x2000>,

		      <0x0 0x48216000 0x0 0x2000>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

arch/arm/boot/dts/ecx-2000.dts

+1 −1
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ 
			interrupt-controller;

			interrupts = <1 9 0xf04>;

			reg = <0xfff11000 0x1000>,

			      <0xfff12000 0x1000>,

			      <0xfff12000 0x2000>,

			      <0xfff14000 0x2000>,

			      <0xfff16000 0x2000>;

		};

arch/arm/boot/dts/exynos3250.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ 
			#interrupt-cells = <3>;

			interrupt-controller;

			reg = <0x10481000 0x1000>,

			      <0x10482000 0x1000>,

			      <0x10482000 0x2000>,

			      <0x10484000 0x2000>,

			      <0x10486000 0x2000>;

			interrupts = <GIC_PPI 9