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Commit 38705613 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'powerpc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux 

Pull powerpc updates from Michael Ellerman:
 "Highlights include:

   - Support for direct mapped LPC on POWER9, giving Linux direct access
     to devices that may be on there such as a UART.

   - Memory hotplug support for the Power9 Radix MMU.

   - Add new AUX vectors describing the processor's cache geometry, to
     be used by glibc.

   - The ability for a guest to ask the hypervisor to resize the guest's
     hash table, and in addition support for doing so automatically when
     memory is hotplugged into/out-of the guest. This allows the hash
     table to be sized based on the current memory usage of the guest,
     rather than the maximum possible memory usage.

   - Implementation of optprobes (kprobe optimisation) for powerpc.

  In addition there's the topic branch shared with the KVM tree, which
  includes support for guests to use the Radix MMU on Power9.

  Thanks to:
    Alistair Popple, Andrew Donnellan, Aneesh Kumar K.V, Anju T, Anton
    Blanchard, Benjamin Herrenschmidt, Chris Packham, Daniel Axtens,
    Daniel Borkmann, David Gibson, Finn Thain, Gautham R. Shenoy, Gavin
    Shan, Greg Kurz, Joel Stanley, John Allen, Madhavan Srinivasan,
    Mahesh Salgaonkar, Markus Elfring, Michael Neuling, Nathan Fontenot,
    Naveen N. Rao, Nicholas Piggin, Paul Mackerras, Ravi Bangoria, Reza
    Arbab, Shailendra Singh, Vaibhav Jain, Wei Yongjun"

* tag 'powerpc-4.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (129 commits)
  powerpc/mm/radix: Skip ptesync in pte update helpers
  powerpc/mm/radix: Use ptep_get_and_clear_full when clearing pte for full mm
  powerpc/mm/radix: Update pte update sequence for pte clear case
  powerpc/mm: Update PROTFAULT handling in the page fault path
  powerpc/xmon: Fix data-breakpoint
  powerpc/mm: Fix build break with BOOK3S_64=n and MEMORY_HOTPLUG=y
  powerpc/mm: Fix build break when CMA=n && SPAPR_TCE_IOMMU=y
  powerpc/mm: Fix build break with RADIX=y & HUGETLBFS=n
  powerpc/pseries: Fix typo in parameter description
  powerpc/kprobes: Remove kprobe_exceptions_notify()
  kprobes: Introduce weak variant of kprobe_exceptions_notify()
  powerpc/ftrace: Fix confusing help text for DISABLE_MPROFILE_KERNEL
  powerpc/powernv: Fix opal_exit tracepoint opcode
  powerpc: Add a prototype for mcount() so it can be versioned
  powerpc: Drop GPL from of_node_to_nid() export to match other arches
  powerpc/kprobes: Optimize kprobe in kretprobe_trampoline()
  powerpc/kprobes: Implement Optprobes
  powerpc/kprobes: Fixes for kprobe_lookup_name() on BE
  powerpc: Add helper to check if offset is within relative branch range
  powerpc/bpf: Introduce __PPC_SH64()
  ...
parents ff47d8c0 438e69b5

Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt

+40 −2
Original line number Diff line number Diff line
@@ -5,8 +5,46 @@ The cache bindings explained below are ePAPR compliant 


Required Properties:



- compatible	: Should include "fsl,chip-l2-cache-controller" and "cache"

		  where chip is the processor (bsc9132, npc8572 etc.)

- compatible	: Should include one of the following:

		  "fsl,8540-l2-cache-controller"

		  "fsl,8541-l2-cache-controller"

		  "fsl,8544-l2-cache-controller"

		  "fsl,8548-l2-cache-controller"

		  "fsl,8555-l2-cache-controller"

		  "fsl,8568-l2-cache-controller"

		  "fsl,b4420-l2-cache-controller"

		  "fsl,b4860-l2-cache-controller"

		  "fsl,bsc9131-l2-cache-controller"

		  "fsl,bsc9132-l2-cache-controller"

		  "fsl,c293-l2-cache-controller"

		  "fsl,mpc8536-l2-cache-controller"

		  "fsl,mpc8540-l2-cache-controller"

		  "fsl,mpc8541-l2-cache-controller"

		  "fsl,mpc8544-l2-cache-controller"

		  "fsl,mpc8548-l2-cache-controller"

		  "fsl,mpc8555-l2-cache-controller"

		  "fsl,mpc8560-l2-cache-controller"

		  "fsl,mpc8568-l2-cache-controller"

		  "fsl,mpc8569-l2-cache-controller"

		  "fsl,mpc8572-l2-cache-controller"

		  "fsl,p1010-l2-cache-controller"

		  "fsl,p1011-l2-cache-controller"

		  "fsl,p1012-l2-cache-controller"

		  "fsl,p1013-l2-cache-controller"

		  "fsl,p1014-l2-cache-controller"

		  "fsl,p1015-l2-cache-controller"

		  "fsl,p1016-l2-cache-controller"

		  "fsl,p1020-l2-cache-controller"

		  "fsl,p1021-l2-cache-controller"

		  "fsl,p1022-l2-cache-controller"

		  "fsl,p1023-l2-cache-controller"

		  "fsl,p1024-l2-cache-controller"

		  "fsl,p1025-l2-cache-controller"

		  "fsl,p2010-l2-cache-controller"

		  "fsl,p2020-l2-cache-controller"

		  "fsl,t2080-l2-cache-controller"

		  "fsl,t4240-l2-cache-controller"

		  and "cache".

- reg		: Address and size of L2 cache controller registers

- cache-size	: Size of the entire L2 cache

- interrupts	: Error interrupt of L2 controller

Documentation/devicetree/bindings/powerpc/opal/power-mgt.txt

0 → 100644
+118 −0
Original line number Diff line number Diff line 
IBM Power-Management Bindings

=============================



Linux running on baremetal POWER machines has access to the processor

idle states. The description of these idle states is exposed via the

node @power-mgt in the device-tree by the firmware.



Definitions:

----------------

Typically each idle state has the following associated properties:



- name: The name of the idle state as defined by the firmware.



- flags: indicating some aspects of this idle states such as the

         extent of state-loss, whether timebase is stopped on this

         idle states and so on. The flag bits are as follows:



- exit-latency: The latency involved in transitioning the state of the

		CPU from idle to running.



- target-residency: The minimum time that the CPU needs to reside in

		    this idle state in order to accrue power-savings

		    benefit.



Properties

----------------

The following properties provide details about the idle states. These

properties are exposed as arrays. Each entry in the property array

provides the value of that property for the idle state associated with

the array index of that entry.



If idle-states are defined, then the properties

"ibm,cpu-idle-state-names" and "ibm,cpu-idle-state-flags" are

required. The other properties are required unless mentioned

otherwise. The length of all the property arrays must be the same.



- ibm,cpu-idle-state-names:

	Array of strings containing the names of the idle states.



- ibm,cpu-idle-state-flags:

	Array of unsigned 32-bit values containing the values of the

	flags associated with the the aforementioned idle-states. The

	flag bits are as follows:

		0x00000001 /* Decrementer would stop */

		0x00000002 /* Needs timebase restore */

		0x00001000 /* Restore GPRs like nap */

		0x00002000 /* Restore hypervisor resource from PACA pointer */

		0x00004000 /* Program PORE to restore PACA pointer */

		0x00010000 /* This is a nap state (POWER7,POWER8) */

		0x00020000 /* This is a fast-sleep state (POWER8)*/

		0x00040000 /* This is a winkle state (POWER8) */

		0x00080000 /* This is a fast-sleep state which requires a */

			   /* software workaround for restoring the */

			   /* timebase (POWER8) */

		0x00800000 /* This state uses SPR PMICR instruction */

			   /* (POWER8)*/

		0x00100000 /* This is a fast stop state (POWER9) */

		0x00200000 /* This is a deep-stop state (POWER9) */



- ibm,cpu-idle-state-latencies-ns:

	Array of unsigned 32-bit values containing the values of the

	exit-latencies (in ns) for the idle states in

	ibm,cpu-idle-state-names.



- ibm,cpu-idle-state-residency-ns:

	Array of unsigned 32-bit values containing the values of the

	target-residency (in ns) for the idle states in

	ibm,cpu-idle-state-names. On POWER8 this is an optional

	property. If the property is absent, the target residency for

	the "Nap", "FastSleep" are defined to 10000 and 300000000

	respectively by the kernel. On POWER9 this property is required.



- ibm,cpu-idle-state-psscr:

	Array of unsigned 64-bit values containing the values for the

	PSSCR for each of the idle states in ibm,cpu-idle-state-names.

	This property is required on POWER9 and absent on POWER8.



- ibm,cpu-idle-state-psscr-mask:

	Array of unsigned 64-bit values containing the masks

	indicating which psscr fields are set in the corresponding

	entries of ibm,cpu-idle-state-psscr. This property is

	required on POWER9 and absent on POWER8.



	Whenever the firmware sets an entry in

	ibm,cpu-idle-state-psscr-mask value to 0xf, it implies that

	only the Requested Level (RL) field of the corresponding entry

	in ibm,cpu-idle-state-psscr should be considered by the

	kernel. For such idle states, the kernel would set the

	remaining fields of the psscr to the following sane-default

	values.



		- ESL and EC bits are to 1. So wakeup from any stop

		  state will be at vector 0x100.



		- MTL and PSLL are set to the maximum allowed value as

		  per the ISA, i.e. 15.



		- The Transition Rate, TR is set to the Maximum value

                  3.



	For all the other values of the entry in

	ibm,cpu-idle-state-psscr-mask, the kernel expects all the

	psscr fields of the corresponding entry in

	ibm,cpu-idle-state-psscr to be correctly set by the firmware.



- ibm,cpu-idle-state-pmicr:

	Array of unsigned 64-bit values containing the pmicr values

	for the idle states in ibm,cpu-idle-state-names. This 64-bit

	register value is to be set in pmicr for the corresponding

	state if the flag indicates that pmicr SPR should be set. This

	is an optional property on POWER8 and is absent on

	POWER9.



- ibm,cpu-idle-state-pmicr-mask:

	Array of unsigned 64-bit values containing the mask indicating

	which of the fields of the PMICR are set in the corresponding

	entries in ibm,cpu-idle-state-pmicr. This is an optional

	property on POWER8 and is absent on POWER9.

Documentation/virtual/kvm/api.txt

+83 −0
Original line number Diff line number Diff line
@@ -3201,6 +3201,71 @@ struct kvm_reinject_control { 
pit_reinject = 0 (!reinject mode) is recommended, unless running an old

operating system that uses the PIT for timing (e.g. Linux 2.4.x).



4.99 KVM_PPC_CONFIGURE_V3_MMU



Capability: KVM_CAP_PPC_RADIX_MMU or KVM_CAP_PPC_HASH_MMU_V3

Architectures: ppc

Type: vm ioctl

Parameters: struct kvm_ppc_mmuv3_cfg (in)

Returns: 0 on success,

         -EFAULT if struct kvm_ppc_mmuv3_cfg cannot be read,

         -EINVAL if the configuration is invalid



This ioctl controls whether the guest will use radix or HPT (hashed

page table) translation, and sets the pointer to the process table for

the guest.



struct kvm_ppc_mmuv3_cfg {

	__u64	flags;

	__u64	process_table;

};



There are two bits that can be set in flags; KVM_PPC_MMUV3_RADIX and

KVM_PPC_MMUV3_GTSE.  KVM_PPC_MMUV3_RADIX, if set, configures the guest

to use radix tree translation, and if clear, to use HPT translation.

KVM_PPC_MMUV3_GTSE, if set and if KVM permits it, configures the guest

to be able to use the global TLB and SLB invalidation instructions;

if clear, the guest may not use these instructions.



The process_table field specifies the address and size of the guest

process table, which is in the guest's space.  This field is formatted

as the second doubleword of the partition table entry, as defined in

the Power ISA V3.00, Book III section 5.7.6.1.



4.100 KVM_PPC_GET_RMMU_INFO



Capability: KVM_CAP_PPC_RADIX_MMU

Architectures: ppc

Type: vm ioctl

Parameters: struct kvm_ppc_rmmu_info (out)

Returns: 0 on success,

	 -EFAULT if struct kvm_ppc_rmmu_info cannot be written,

	 -EINVAL if no useful information can be returned



This ioctl returns a structure containing two things: (a) a list

containing supported radix tree geometries, and (b) a list that maps

page sizes to put in the "AP" (actual page size) field for the tlbie

(TLB invalidate entry) instruction.



struct kvm_ppc_rmmu_info {

	struct kvm_ppc_radix_geom {

		__u8	page_shift;

		__u8	level_bits[4];

		__u8	pad[3];

	}	geometries[8];

	__u32	ap_encodings[8];

};



The geometries[] field gives up to 8 supported geometries for the

radix page table, in terms of the log base 2 of the smallest page

size, and the number of bits indexed at each level of the tree, from

the PTE level up to the PGD level in that order.  Any unused entries

will have 0 in the page_shift field.



The ap_encodings gives the supported page sizes and their AP field

encodings, encoded with the AP value in the top 3 bits and the log

base 2 of the page size in the bottom 6 bits.



5. The kvm_run structure

------------------------
@@ -3942,3 +4007,21 @@ In order to use SynIC, it has to be activated by setting this 
capability via KVM_ENABLE_CAP ioctl on the vcpu fd. Note that this

will disable the use of APIC hardware virtualization even if supported

by the CPU, as it's incompatible with SynIC auto-EOI behavior.



8.3 KVM_CAP_PPC_RADIX_MMU



Architectures: ppc



This capability, if KVM_CHECK_EXTENSION indicates that it is

available, means that that the kernel can support guests using the

radix MMU defined in Power ISA V3.00 (as implemented in the POWER9

processor).



8.4 KVM_CAP_PPC_HASH_MMU_V3



Architectures: ppc



This capability, if KVM_CHECK_EXTENSION indicates that it is

available, means that that the kernel can support guests using the

hashed page table MMU defined in Power ISA V3.00 (as implemented in

the POWER9 processor), including in-memory segment tables.

arch/m68k/include/asm/macintosh.h

+1 −1
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ struct mac_model 


#define MAC_ADB_NONE		0

#define MAC_ADB_II		1

#define MAC_ADB_IISI		2

#define MAC_ADB_EGRET		2

#define MAC_ADB_CUDA		3

#define MAC_ADB_PB1		4

#define MAC_ADB_PB2		5

arch/m68k/mac/config.c

+9 −9
Original line number Diff line number Diff line
@@ -286,7 +286,7 @@ static struct mac_model mac_data_table[] = { 
	}, {

		.ident		= MAC_MODEL_IISI,

		.name		= "IIsi",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_OLD,

		.scc_type	= MAC_SCC_II,
@@ -295,7 +295,7 @@ static struct mac_model mac_data_table[] = { 
	}, {

		.ident		= MAC_MODEL_IIVI,

		.name		= "IIvi",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,
@@ -304,7 +304,7 @@ static struct mac_model mac_data_table[] = { 
	}, {

		.ident		= MAC_MODEL_IIVX,

		.name		= "IIvx",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,
@@ -319,7 +319,7 @@ static struct mac_model mac_data_table[] = { 
	{

		.ident		= MAC_MODEL_CLII,

		.name		= "Classic II",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,
@@ -352,7 +352,7 @@ static struct mac_model mac_data_table[] = { 
	{

		.ident		= MAC_MODEL_LC,

		.name		= "LC",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,
@@ -361,7 +361,7 @@ static struct mac_model mac_data_table[] = { 
	}, {

		.ident		= MAC_MODEL_LCII,

		.name		= "LC II",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,
@@ -370,7 +370,7 @@ static struct mac_model mac_data_table[] = { 
	}, {

		.ident		= MAC_MODEL_LCIII,

		.name		= "LC III",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,
@@ -498,7 +498,7 @@ static struct mac_model mac_data_table[] = { 
	{

		.ident		= MAC_MODEL_P460,

		.name		= "Performa 460",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,
@@ -575,7 +575,7 @@ static struct mac_model mac_data_table[] = { 
	}, {

		.ident		= MAC_MODEL_P600,

		.name		= "Performa 600",

		.adb_type	= MAC_ADB_IISI,

		.adb_type	= MAC_ADB_EGRET,

		.via_type	= MAC_VIA_IICI,

		.scsi_type	= MAC_SCSI_LC,

		.scc_type	= MAC_SCC_II,