drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. (385db982) · Commits · e / devices / android_kernel_oneplus_sm7250

Driver’s CPU access to GTT is via the GTTMMADR BAR. The current HW implementation of that BAR is to only support <= DW (and maybe QW) writes—not 16/32/64B writes that could occur with WC and/or SSE/AVX moves. GTTMMADR must be marked uncacheable (UC). Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry). v2: Get clarification on the reasons and spec is getting updated to reflect it now. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Suggested-by:

Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by:

Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:

Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829230907.21363-1-rodrigo.vivi@intel.com

drivers/gpu/drm/i915/i915_gem_gtt.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -2790,13 +2790,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
		phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;

		/*
		* On BXT writes larger than 64 bit to the GTT pagetable range will be
		* dropped. For WC mappings in general we have 64 byte burst writes
		* when the WC buffer is flushed, so we can't use it, but have to
		* On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
		* will be dropped. For WC mappings in general we have 64 byte burst
		* writes when the WC buffer is flushed, so we can't use it, but have to
		* resort to an uncached mapping. The WC issue is easily caught by the
		* readback check when writing GTT PTE entries.
		*/
		if (IS_GEN9_LP(dev_priv))
		if (IS_GEN9_LP(dev_priv) \|\| INTEL_GEN(dev_priv) >= 10)
		ggtt->gsm = ioremap_nocache(phys_addr, size);
		else
		ggtt->gsm = ioremap_wc(phys_addr, size);