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Commit 378506a7 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx: create a common bitmask function (v2) 



The same function was duplicated in all the gfx IPs. Use
a single implementation for all.

v2: use static inline (Alex Xie)

Reviewed-by: default avatarAlex Xie <AlexBin.Xie@amd.com>
Suggested-by: default avatarAndres Rodriguez <andresx7@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 943c05bd

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+13 −0
Original line number Diff line number Diff line
@@ -30,4 +30,17 @@ void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg); 
void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,

		unsigned max_sh);



/**

 * amdgpu_gfx_create_bitmask - create a bitmask

 *

 * @bit_width: length of the mask

 *

 * create a variable length bit mask.

 * Returns the bitmask.

 */

static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)

{

	return (u32)((1ULL << bit_width) - 1);

}



#endif

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+3 −8
Original line number Diff line number Diff line
@@ -1114,11 +1114,6 @@ static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 
	WREG32(mmGRBM_GFX_INDEX, data);

}



static u32 gfx_v6_0_create_bitmask(u32 bit_width)

{

	return (u32)(((u64)1 << bit_width) - 1);

}



static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)

{

	u32 data, mask;
@@ -1128,7 +1123,7 @@ static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev) 


	data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);



	mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_backends_per_se/

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/

					 adev->gfx.config.max_sh_per_se);



	return ~data & mask;
@@ -1331,7 +1326,7 @@ static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev) 
	data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |

		RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);



	mask = gfx_v6_0_create_bitmask(adev->gfx.config.max_cu_per_sh);

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);

	return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;

}

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+3 −16
Original line number Diff line number Diff line
@@ -1607,19 +1607,6 @@ static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 
	WREG32(mmGRBM_GFX_INDEX, data);

}



/**

 * gfx_v7_0_create_bitmask - create a bitmask

 *

 * @bit_width: length of the mask

 *

 * create a variable length bit mask (CIK).

 * Returns the bitmask.

 */

static u32 gfx_v7_0_create_bitmask(u32 bit_width)

{

	return (u32)((1ULL << bit_width) - 1);

}



/**

 * gfx_v7_0_get_rb_active_bitmap - computes the mask of enabled RBs

 *
@@ -1638,7 +1625,7 @@ static u32 gfx_v7_0_get_rb_active_bitmap(struct amdgpu_device *adev) 
	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;

	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;



	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

					 adev->gfx.config.max_sh_per_se);



	return (~data) & mask;
@@ -4157,7 +4144,7 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 
	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;

	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;



	mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);



	return (~data) & mask;

}

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+3 −8
Original line number Diff line number Diff line
@@ -3635,11 +3635,6 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, 
	WREG32(mmGRBM_GFX_INDEX, data);

}



static u32 gfx_v8_0_create_bitmask(u32 bit_width)

{

	return (u32)((1ULL << bit_width) - 1);

}



static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)

{

	u32 data, mask;
@@ -3649,7 +3644,7 @@ static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) 


	data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);



	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

					 adev->gfx.config.max_sh_per_se);



	return (~data) & mask;
@@ -7150,7 +7145,7 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev) 
	data =  RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |

		RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);



	mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);



	return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;

}

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+3 −8
Original line number Diff line number Diff line
@@ -1698,11 +1698,6 @@ static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh 
	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);

}



static u32 gfx_v9_0_create_bitmask(u32 bit_width)

{

	return (u32)((1ULL << bit_width) - 1);

}



static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)

{

	u32 data, mask;
@@ -1713,7 +1708,7 @@ static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 
	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;

	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;



	mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_backends_per_se /

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /

					 adev->gfx.config.max_sh_per_se);



	return (~data) & mask;
@@ -4609,7 +4604,7 @@ static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 
	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;

	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;



	mask = gfx_v9_0_create_bitmask(adev->gfx.config.max_cu_per_sh);

	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);



	return (~data) & mask;

}