Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 37549196 authored by Taniya Das's avatar Taniya Das Committed by Saurabh Sahu
Browse files

clk: qcom: clk-alpha-pll: Update the steps to slew the Lucid PLL 



When PLL HW_UPDATE_LOGIC_BYPASS bit is not set then PLL can be
updated dynamically by setting the PLL_UPDATE bit in mode register
and hardware would clear the PLL_UPDATE automatically when
PLL_ACK_LATCH is asserted.

Change-Id: I1c568c9fdd37a554d71fc5c3d840a71e983baf60
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 6d9e903c

drivers/clk/qcom/clk-alpha-pll.c

+7 −1
Original line number Diff line number Diff line
@@ -2310,7 +2310,13 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, 
	/* Wait for 2 reference cycles before checking the ACK bit. */

	udelay(1);

	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);

	if (!(regval & ALPHA_PLL_ACK_LATCH)) {

	if (!(regval & PLL_UPDATE_BYPASS)) {

		ret = wait_for_pll_update(pll);

		if (ret)

			WARN_CLK(hw->core, clk_hw_get_name(hw), 1,

				"PLL Update clear failed\n");

		return ret;

	} else if (!(regval & ALPHA_PLL_ACK_LATCH)) {

		WARN_CLK(hw->core, clk_hw_get_name(hw), 1,

				"PLL latch failed. Output may be unstable!\n");

		return -EINVAL;