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Commit 37507717 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 perf updates from Ingo Molnar:
 "This series tightens up RDPMC permissions: currently even highly
  sandboxed x86 execution environments (such as seccomp) have permission
  to execute RDPMC, which may leak various perf events / PMU state such
  as timing information and other CPU execution details.

  This 'all is allowed' RDPMC mode is still preserved as the
  (non-default) /sys/devices/cpu/rdpmc=2 setting.  The new default is
  that RDPMC access is only allowed if a perf event is mmap-ed (which is
  needed to correctly interpret RDPMC counter values in any case).

  As a side effect of these changes CR4 handling is cleaned up in the
  x86 code and a shadow copy of the CR4 value is added.

  The extra CR4 manipulation adds ~ <50ns to the context switch cost
  between rdpmc-capable and rdpmc-non-capable mms"

* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86: Add /sys/devices/cpu/rdpmc=2 to allow rdpmc for all tasks
  perf/x86: Only allow rdpmc if a perf_event is mapped
  perf: Pass the event to arch_perf_update_userpage()
  perf: Add pmu callbacks to track event mapping and unmapping
  x86: Add a comment clarifying LDT context switching
  x86: Store a per-cpu shadow copy of CR4
  x86: Clean up cr4 manipulation
parents a68fb483 a6673429

arch/x86/include/asm/mmu.h

+2 −0
Original line number Diff line number Diff line
@@ -19,6 +19,8 @@ typedef struct { 


	struct mutex lock;

	void __user *vdso;



	atomic_t perf_rdpmc_allowed;	/* nonzero if rdpmc is allowed */

} mm_context_t;



#ifdef CONFIG_SMP

arch/x86/include/asm/mmu_context.h

+27 −6
Original line number Diff line number Diff line
@@ -18,6 +18,21 @@ static inline void paravirt_activate_mm(struct mm_struct *prev, 
}

#endif	/* !CONFIG_PARAVIRT */



#ifdef CONFIG_PERF_EVENTS

extern struct static_key rdpmc_always_available;



static inline void load_mm_cr4(struct mm_struct *mm)

{

	if (static_key_true(&rdpmc_always_available) ||

	    atomic_read(&mm->context.perf_rdpmc_allowed))

		cr4_set_bits(X86_CR4_PCE);

	else

		cr4_clear_bits(X86_CR4_PCE);

}

#else

static inline void load_mm_cr4(struct mm_struct *mm) {}

#endif



/*

 * Used for LDT copy/destruction.

 */
@@ -52,15 +67,20 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
		/* Stop flush ipis for the previous mm */

		cpumask_clear_cpu(cpu, mm_cpumask(prev));



		/* Load per-mm CR4 state */

		load_mm_cr4(next);



		/*

		 * Load the LDT, if the LDT is different.

		 *

		 * It's possible leave_mm(prev) has been called.  If so,

		 * then prev->context.ldt could be out of sync with the

		 * LDT descriptor or the LDT register.  This can only happen

		 * if prev->context.ldt is non-null, since we never free

		 * an LDT.  But LDTs can't be shared across mms, so

		 * prev->context.ldt won't be equal to next->context.ldt.

		 * It's possible that prev->context.ldt doesn't match

		 * the LDT register.  This can happen if leave_mm(prev)

		 * was called and then modify_ldt changed

		 * prev->context.ldt but suppressed an IPI to this CPU.

		 * In this case, prev->context.ldt != NULL, because we

		 * never free an LDT while the mm still exists.  That

		 * means that next->context.ldt != prev->context.ldt,

		 * because mms never share an LDT.

		 */

		if (unlikely(prev->context.ldt != next->context.ldt))

			load_LDT_nolock(&next->context);
@@ -85,6 +105,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 
			 */

			load_cr3(next->pgd);

			trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);

			load_mm_cr4(next);

			load_LDT_nolock(&next->context);

		}

	}

arch/x86/include/asm/paravirt.h

+3 −3
Original line number Diff line number Diff line
@@ -80,16 +80,16 @@ static inline void write_cr3(unsigned long x) 
	PVOP_VCALL1(pv_mmu_ops.write_cr3, x);

}



static inline unsigned long read_cr4(void)

static inline unsigned long __read_cr4(void)

{

	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4);

}

static inline unsigned long read_cr4_safe(void)

static inline unsigned long __read_cr4_safe(void)

{

	return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe);

}



static inline void write_cr4(unsigned long x)

static inline void __write_cr4(unsigned long x)

{

	PVOP_VCALL1(pv_cpu_ops.write_cr4, x);

}

arch/x86/include/asm/processor.h

+0 −33
Original line number Diff line number Diff line
@@ -579,39 +579,6 @@ static inline void load_sp0(struct tss_struct *tss, 
#define set_iopl_mask native_set_iopl_mask

#endif /* CONFIG_PARAVIRT */



/*

 * Save the cr4 feature set we're using (ie

 * Pentium 4MB enable and PPro Global page

 * enable), so that any CPU's that boot up

 * after us can get the correct flags.

 */

extern unsigned long mmu_cr4_features;

extern u32 *trampoline_cr4_features;



static inline void set_in_cr4(unsigned long mask)

{

	unsigned long cr4;



	mmu_cr4_features |= mask;

	if (trampoline_cr4_features)

		*trampoline_cr4_features = mmu_cr4_features;

	cr4 = read_cr4();

	cr4 |= mask;

	write_cr4(cr4);

}



static inline void clear_in_cr4(unsigned long mask)

{

	unsigned long cr4;



	mmu_cr4_features &= ~mask;

	if (trampoline_cr4_features)

		*trampoline_cr4_features = mmu_cr4_features;

	cr4 = read_cr4();

	cr4 &= ~mask;

	write_cr4(cr4);

}



typedef struct {

	unsigned long		seg;

} mm_segment_t;

arch/x86/include/asm/special_insns.h

+3 −3
Original line number Diff line number Diff line
@@ -137,17 +137,17 @@ static inline void write_cr3(unsigned long x) 
	native_write_cr3(x);

}



static inline unsigned long read_cr4(void)

static inline unsigned long __read_cr4(void)

{

	return native_read_cr4();

}



static inline unsigned long read_cr4_safe(void)

static inline unsigned long __read_cr4_safe(void)

{

	return native_read_cr4_safe();

}



static inline void write_cr4(unsigned long x)

static inline void __write_cr4(unsigned long x)

{

	native_write_cr4(x);

}