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Commit 36e6b912 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amd/powerplay: enable DiDt feature for polaris10/11. 



DIDT is a power saving feature which helps limit power
consumption in order to hit a target power allocation.

v1: delete temp file added accidentally.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c0bcc4ec

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

+13 −4
Original line number Diff line number Diff line
@@ -2668,6 +2668,10 @@ int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 
	PP_ASSERT_WITH_CODE((0 == tmp_result),

			"Failed to enable deep sleep master switch!", result = tmp_result);



	tmp_result = polaris10_enable_didt_config(hwmgr);

	PP_ASSERT_WITH_CODE((tmp_result == 0),

			"Failed to enable deep sleep master switch!", result = tmp_result);



	tmp_result = polaris10_start_dpm(hwmgr);

	PP_ASSERT_WITH_CODE((0 == tmp_result),

			"Failed to start DPM!", result = tmp_result);
@@ -2807,13 +2811,13 @@ int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr) 
					PHM_PlatformCaps_DynamicUVDState);



	/* power tune caps Assume disabled */

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

						PHM_PlatformCaps_SQRamping);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

						PHM_PlatformCaps_DBRamping);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

						PHM_PlatformCaps_TDRamping);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

						PHM_PlatformCaps_TCPRamping);



	if (hwmgr->powercontainment_enabled)
@@ -3640,6 +3644,7 @@ static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 
				    hwmgr->platform_descriptor.platformCaps,

				    PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);





	disable_mclk_switching = (1 < info.display_count) ||

				    disable_mclk_switching_for_frame_lock;
@@ -4616,6 +4621,8 @@ static int polaris10_notify_smc_display(struct pp_hwmgr *hwmgr) 
	return (smum_send_msg_to_smc(hwmgr->smumgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;

}







static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)

{

	int tmp_result, result = 0;
@@ -4724,6 +4731,7 @@ int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwm 
	if (num_active_displays > 1)  /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */

		polaris10_notify_smc_display_change(hwmgr, false);





	return 0;

}
@@ -4773,6 +4781,7 @@ int polaris10_program_display_gap(struct pp_hwmgr *hwmgr) 


	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));





	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c

+531 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h

+10 −1
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ enum polaris10_pt_config_reg_type { 
	POLARIS10_CONFIGREG_MMR = 0,

	POLARIS10_CONFIGREG_SMC_IND,

	POLARIS10_CONFIGREG_DIDT_IND,

	POLARIS10_CONFIGREG_GC_CAC_IND,

	POLARIS10_CONFIGREG_CACHE,

	POLARIS10_CONFIGREG_MAX

};
@@ -49,6 +50,14 @@ enum polaris10_pt_config_reg_type { 
#define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002

#define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004



#define ixGC_CAC_CNTL 0x0000

#define ixDIDT_SQ_STALL_CTRL 0x0004

#define  ixDIDT_SQ_TUNING_CTRL 0x0005

#define ixDIDT_TD_STALL_CTRL 0x0044

#define ixDIDT_TD_TUNING_CTRL 0x0045

#define ixDIDT_TCP_STALL_CTRL 0x0064

#define ixDIDT_TCP_TUNING_CTRL 0x0065



struct polaris10_pt_config_reg {

	uint32_t                           offset;

	uint32_t                           mask;
@@ -80,6 +89,6 @@ int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr); 
int polaris10_disable_power_containment(struct pp_hwmgr *hwmgr);

int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);

int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr);



int polaris10_enable_didt_config(struct pp_hwmgr *hwmgr);

#endif  /* POLARIS10_POWERTUNE_H */