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Commit 36cc8b96 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Convert intel_rc6_residency_us to ns



Will be used for exposing the PMU counters.

v2:
 * Move intel_runtime_pm_get/put to the callers. (Chris Wilson)
 * Restore full unit conversion precision.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-8-tvrtko.ursulin@linux.intel.com
parent 0cd4684d
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+7 −1
Original line number Diff line number Diff line
@@ -4228,11 +4228,17 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,

int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
			   const i915_reg_t reg);

u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);

static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
					 const i915_reg_t reg)
{
	return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}

#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

+7 −2
Original line number Diff line number Diff line
@@ -42,8 +42,13 @@ static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
static u32 calc_residency(struct drm_i915_private *dev_priv,
			  i915_reg_t reg)
{
	return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg),
				     1000);
	u64 res;

	intel_runtime_pm_get(dev_priv);
	res = intel_rc6_residency_us(dev_priv, reg);
	intel_runtime_pm_put(dev_priv);

	return DIV_ROUND_CLOSEST_ULL(res, 1000);
}

static ssize_t
+13 −14
Original line number Diff line number Diff line
@@ -9437,36 +9437,35 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
	return lower | (u64)upper << 8;
}

u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
			   const i915_reg_t reg)
{
	u64 time_hw, units, div;
	u64 time_hw;
	u32 mul, div;

	if (!intel_rc6_enabled())
		return 0;

	intel_runtime_pm_get(dev_priv);

	/* On VLV and CHV, residency time is in CZ units rather than 1.28us */
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
		units = 1000;
		mul = 1000000;
		div = dev_priv->czclk_freq;

		time_hw = vlv_residency_raw(dev_priv, reg);
	} else if (IS_GEN9_LP(dev_priv)) {
		units = 1000;
		div = 1200;		/* 833.33ns */

		time_hw = I915_READ(reg);
	} else {
		units = 128000; /* 1.28us */
		div = 100000;
		/* 833.33ns units on Gen9LP, 1.28us elsewhere. */
		if (IS_GEN9_LP(dev_priv)) {
			mul = 10000;
			div = 12;
		} else {
			mul = 1280;
			div = 1;
		}

		time_hw = I915_READ(reg);
	}

	intel_runtime_pm_put(dev_priv);
	return DIV_ROUND_UP_ULL(time_hw * units, div);
	return DIV_ROUND_UP_ULL(time_hw * mul, div);
}

u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)