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Commit 36b10a72 authored by Vladimir Kondratiev's avatar Vladimir Kondratiev Committed by John W. Linville
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wil6210: update target reset to support new HW



Support for new chip revision. Revision read from the
internal register, PCIE config's "revision id" register
do not indicate HW version properly

Signed-off-by: default avatarVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 2232abd5
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+28 −1
Original line number Original line Diff line number Diff line
@@ -230,14 +230,22 @@ void wil_priv_deinit(struct wil6210_priv *wil)


static void wil_target_reset(struct wil6210_priv *wil)
static void wil_target_reset(struct wil6210_priv *wil)
{
{
	int delay = 100;
	u32 baud_rate;
	u32 rev_id;

	wil_dbg_misc(wil, "Resetting...\n");
	wil_dbg_misc(wil, "Resetting...\n");


	/* register read */
#define R(a) ioread32(wil->csr + HOSTADDR(a))
	/* register write */
	/* register write */
#define W(a, v) iowrite32(v, wil->csr + HOSTADDR(a))
#define W(a, v) iowrite32(v, wil->csr + HOSTADDR(a))
	/* register set = read, OR, write */
	/* register set = read, OR, write */
#define S(a, v) iowrite32(ioread32(wil->csr + HOSTADDR(a)) | v, \
#define S(a, v) iowrite32(ioread32(wil->csr + HOSTADDR(a)) | v, \
		wil->csr + HOSTADDR(a))
		wil->csr + HOSTADDR(a))


	wil->hw_version = R(RGF_FW_REV_ID);
	rev_id = wil->hw_version & 0xff;
	/* hpal_perst_from_pad_src_n_mask */
	/* hpal_perst_from_pad_src_n_mask */
	S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(6));
	S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(6));
	/* car_perst_rst_src_n_mask */
	/* car_perst_rst_src_n_mask */
@@ -257,11 +265,30 @@ static void wil_target_reset(struct wil6210_priv *wil)
	W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
	W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);


	W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
	W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
	if (rev_id == 1) {
		W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
		W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
	} else {
		W(RGF_LOS_COUNTER_CTL, BIT(6) | BIT(8));
		W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
	}
	W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
	W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);


	/* wait until device ready. Use baud rate */
	do {
		msleep(1);
		baud_rate = R(RGF_USER_SERIAL_BAUD_RATE);
		if (delay-- < 0) {
			wil_err(wil, "Reset not completed\n");
			return;
		}
	} while (baud_rate != 0x15e);

	if (rev_id == 2)
		W(RGF_LOS_COUNTER_CTL, BIT(8));

	wil_dbg_misc(wil, "Reset completed\n");
	wil_dbg_misc(wil, "Reset completed\n");


#undef R
#undef W
#undef W
#undef S
#undef S
}
}
+2 −0
Original line number Original line Diff line number Diff line
@@ -74,6 +74,8 @@ static int wil_if_pcie_enable(struct wil6210_priv *wil)
	if (rc)
	if (rc)
		goto release_irq;
		goto release_irq;


	wil_info(wil, "HW version: 0x%08x\n", wil->hw_version);

	return 0;
	return 0;


 release_irq:
 release_irq:
+4 −0
Original line number Original line Diff line number Diff line
@@ -74,6 +74,9 @@ struct RGF_ICR {
} __packed;
} __packed;


/* registers - FW addresses */
/* registers - FW addresses */
#define RGF_FW_REV_ID			(0x880a8c) /* chip revision */
#define RGF_USER_SERIAL_BAUD_RATE	(0x880050)
#define RGF_LOS_COUNTER_CTL		(0x882dc4)
#define RGF_USER_USER_SCRATCH_PAD	(0x8802bc)
#define RGF_USER_USER_SCRATCH_PAD	(0x8802bc)
#define RGF_USER_USER_ICR		(0x880b4c) /* struct RGF_ICR */
#define RGF_USER_USER_ICR		(0x880b4c) /* struct RGF_ICR */
	#define BIT_USER_USER_ICR_SW_INT_2	BIT(18)
	#define BIT_USER_USER_ICR_SW_INT_2	BIT(18)
@@ -342,6 +345,7 @@ struct wil6210_priv {
	void __iomem *csr;
	void __iomem *csr;
	ulong status;
	ulong status;
	u32 fw_version;
	u32 fw_version;
	u32 hw_version;
	u8 n_mids; /* number of additional MIDs as reported by FW */
	u8 n_mids; /* number of additional MIDs as reported by FW */
	/* profile */
	/* profile */
	u32 monitor_flags;
	u32 monitor_flags;