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Commit 36ab0467 authored by Yuantian Tang's avatar Yuantian Tang Committed by Stephen Boyd
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clk: qoriq: add more divider clocks support 



More divider clocks are needed by IP. So enlarge the PLL divider
array to accommodate more divider clocks.

Signed-off-by: default avatarTang Yuantian <andy.tang@nxp.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 4fbd8d19

Documentation/devicetree/bindings/clock/qoriq-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ second cell is the clock index for the specified type. 
	2	hwaccel		index (n in CLKCGnHWACSR)

	3	fman		0 for fm1, 1 for fm2

	4	platform pll	0=pll, 1=pll/2, 2=pll/3, 3=pll/4

				4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8

	5	coreclk		must be 0



3. Example

drivers/clk/clk-qoriq.c

+8 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ struct clockgen_pll_div { 
};



struct clockgen_pll {

	struct clockgen_pll_div div[4];

	struct clockgen_pll_div div[8];

};



#define CLKSEL_VALID	1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx) 
		struct clk *clk;

		int ret;



		/*

		 * For platform PLL, there are 8 divider clocks.

		 * For core PLL, there are 4 divider clocks at most.

		 */

		if (idx != PLATFORM_PLL && i >= 4)

			break;



		snprintf(pll->div[i].name, sizeof(pll->div[i].name),

			 "cg-pll%d-div%d", idx, i + 1);