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Commit 3681bafe authored by Daniel Lezcano's avatar Daniel Lezcano Committed by Kukjin Kim
Browse files

ARM: EXYNOS: Move the AFTR state function into pm.c 



In order to remove depedency on pm code, let's move the 'exynos_enter_aftr'
function into the pm.c file as well as the other helper functions.

Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 712bb69e

arch/arm/mach-exynos/common.h

+1 −0
Original line number Diff line number Diff line
@@ -69,5 +69,6 @@ extern int exynos_cpu_power_state(int cpu); 
extern void exynos_cluster_power_down(int cluster);

extern void exynos_cluster_power_up(int cluster);

extern int  exynos_cluster_power_state(int cluster);

extern void exynos_enter_aftr(void);



#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */

arch/arm/mach-exynos/cpuidle.c

+0 −29
Original line number Diff line number Diff line
@@ -31,35 +31,6 @@ 
#include "common.h"

#include "regs-pmu.h"



#define REG_DIRECTGO_ADDR	(samsung_rev() == EXYNOS4210_REV_1_1 ? \

			S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \

			(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))

#define REG_DIRECTGO_FLAG	(samsung_rev() == EXYNOS4210_REV_1_1 ? \

			S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \

			(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))



#define S5P_CHECK_AFTR		0xFCBA0D10



/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */

static void exynos_set_wakeupmask(long mask)

{

	__raw_writel(mask, S5P_WAKEUP_MASK);

}



static void exynos_cpu_set_boot_vector(long flags)

{

	__raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);

	__raw_writel(flags, REG_DIRECTGO_FLAG);

}



static void exynos_enter_aftr(void)

{

	exynos_set_wakeupmask(0x0000ff3e);

	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);

	/* Set value of power down register for aftr mode */

	exynos_sys_powerdown_conf(SYS_AFTR);

}



static int idle_finisher(unsigned long flags)

{

	exynos_enter_aftr();

arch/arm/mach-exynos/pm.c

+29 −0
Original line number Diff line number Diff line
@@ -167,6 +167,35 @@ int exynos_cluster_power_state(int cluster) 
			S5P_CORE_LOCAL_PWR_EN);

}



#define EXYNOS_BOOT_VECTOR_ADDR	(samsung_rev() == EXYNOS4210_REV_1_1 ? \

			S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \

			(S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))

#define EXYNOS_BOOT_VECTOR_FLAG	(samsung_rev() == EXYNOS4210_REV_1_1 ? \

			S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \

			(S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))



#define S5P_CHECK_AFTR 0xFCBA0D10



/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */

static void exynos_set_wakeupmask(long mask)

{

	__raw_writel(mask, S5P_WAKEUP_MASK);

}



static void exynos_cpu_set_boot_vector(long flags)

{

	__raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);

	__raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);

}



void exynos_enter_aftr(void)

{

	exynos_set_wakeupmask(0x0000ff3e);

	exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);

	/* Set value of power down register for aftr mode */

	exynos_sys_powerdown_conf(SYS_AFTR);

}



/* For Cortex-A9 Diagnostic and Power control register */

static unsigned int save_arm_register[2];