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Commit 3639fa68 authored by Zeyu Fan's avatar Zeyu Fan Committed by Alex Deucher
Browse files

drm/amd/display: Clean up some DCN1 guards 



Signed-off-by: default avatarZeyu Fan <Zeyu.Fan@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f4d5abf5

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( 
		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

#endif



	case DCE_VERSION_12_0:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

drivers/gpu/drm/amd/display/dc/core/dc.c

+1 −1
Original line number Diff line number Diff line
@@ -1109,7 +1109,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) 


	/* 3rd param should be true, temp w/a for RV*/

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version != DCN_VERSION_1_0);

	core_dc->hwss.set_bandwidth(core_dc, context, core_dc->ctx->dce_version < DCN_VERSION_1_0);

#else

	core_dc->hwss.set_bandwidth(core_dc, context, true);

#endif

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+2 −0
Original line number Diff line number Diff line
@@ -120,6 +120,8 @@ struct resource_pool *dc_create_resource_pool( 
			num_virtual_links, dc);

		break;

#endif





	default:

		break;

	}

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+2 −0
Original line number Diff line number Diff line
@@ -589,6 +589,7 @@ static uint32_t dce110_get_pix_clk_dividers( 
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case DCN_VERSION_1_0:

#endif



		dce112_get_pix_clk_dividers_helper(clk_src,

				pll_settings, pix_clk_params);

		break;
@@ -901,6 +902,7 @@ static bool dce110_program_pix_clk( 
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

	case DCN_VERSION_1_0:

#endif



		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {

			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =

							pll_settings->use_external_clk;

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

+1 −1
Original line number Diff line number Diff line
@@ -614,7 +614,7 @@ static bool dce_apply_clock_voltage_request( 
	}

	if (send_request) {

#if defined(CONFIG_DRM_AMD_DC_DCN1_0)

		if (clk->ctx->dce_version == DCN_VERSION_1_0) {

		if (clk->ctx->dce_version >= DCN_VERSION_1_0) {

			struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc);

			/*use dcfclk request voltage*/

			clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;